ebit_ten_counter.vhd

来自「数字频率计是一种用来测试周期性变化信号工作频率的装置。其原理是在规定的单位时间（」· VHDL 代码 · 共 74 行

library ieee;     
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ten_counter is
port(clk:in std_logic;
     bcd1:buffer std_logic_vector(3 downto 0);
     preset,en:in std_logic;
     co: out std_logic);
end ten_counter;
architecture rt2 of ten_counter is
signal sen:std_logic;
begin
process(en,clk)
  begin
  sen<=en and clk;
end process;
 process(sen,preset)
   begin
    if preset='1' then
       bcd1<="0000";     
      else
         if sen'event and sen='1' then   --上升沿
           if bcd1="1000" then
            bcd1<=bcd1+'1';
            co<='0';
           elsif bcd1="1001"then
            bcd1<="0000";
            co<='1';
           else
            bcd1<=bcd1+'1';
            
           end if;
         end if; 
      end if;
end process;
end rt2;
---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ebit_ten_counter is
port(clk_test:in std_logic;
     a_bcd,b_bcd,c_bcd,d_bcd,e_bcd,f_bcd,g_bcd,h_bcd:buffer std_logic_vector(3 downto 0);
     clr_ent,cnt_en:in std_logic;
     sco: out std_logic);
end ebit_ten_counter;
ARCHITECTURE a OF ebit_ten_counter IS
	COMPONENT ten_counter
		PORT(clk:in std_logic;
     bcd1:buffer std_logic_vector(3 downto 0);
     preset,en:in std_logic;
     co: out std_logic);
		END COMPONENT;
SIGNAL co1,co2,co3,co4,co5,co6,co7 : STD_LOGIC;
BEGIN
u1:ten_counter
	PORT MAP (clk_test,a_bcd,clr_ent,cnt_en,co1);
u2:ten_counter
	PORT MAP (co1,b_bcd,clr_ent,cnt_en,co2);
u3:ten_counter
	PORT MAP (co2,c_bcd,clr_ent,cnt_en,co3);
u4:ten_counter
	PORT MAP (co3,d_bcd,clr_ent,cnt_en,co4);
u5:ten_counter
	PORT MAP (co4,e_bcd,clr_ent,cnt_en,co5);
u6:ten_counter
	PORT MAP (co5,f_bcd,clr_ent,cnt_en,co6);
u7:ten_counter
	PORT MAP (co6,g_bcd,clr_ent,cnt_en,co7);
u8:ten_counter
	PORT MAP (co7,h_bcd,clr_ent,cnt_en,sco);
END a;