📄 top.rpt
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- 1 - D 15 OR2 0 3 0 1 |DISPLAY:1|:610
- 3 - E 21 OR2 0 3 0 1 |DISPLAY:1|:613
- 5 - E 21 OR2 0 3 0 1 |DISPLAY:1|:616
- 7 - E 21 OR2 0 3 0 1 |DISPLAY:1|:619
- 6 - D 24 OR2 0 3 0 1 |DISPLAY:1|:628
- 7 - D 24 OR2 0 3 0 1 |DISPLAY:1|:631
- 1 - D 24 OR2 0 3 0 1 |DISPLAY:1|:634
- 3 - E 20 OR2 0 3 0 1 |DISPLAY:1|:637
- 5 - E 20 OR2 0 3 0 1 |DISPLAY:1|:640
- 7 - E 20 OR2 0 3 0 1 |DISPLAY:1|:643
- 6 - D 17 OR2 0 3 0 1 |DISPLAY:1|:652
- 7 - D 17 OR2 0 3 0 1 |DISPLAY:1|:655
- 1 - D 17 OR2 0 3 0 1 |DISPLAY:1|:658
- 3 - E 13 OR2 0 3 0 1 |DISPLAY:1|:661
- 5 - E 13 OR2 0 3 0 1 |DISPLAY:1|:664
- 7 - E 13 OR2 0 3 0 1 |DISPLAY:1|:667
- 1 - B 23 AND2 0 4 0 2 |DISPLAY:1|:869
- 3 - B 23 OR2 ! 0 4 0 2 |DISPLAY:1|:874
- 3 - B 17 AND2 0 4 0 1 |DISPLAY:1|:879
- 2 - B 17 OR2 ! 0 4 0 2 |DISPLAY:1|:889
- 5 - B 23 OR2 ! 0 4 0 1 |DISPLAY:1|:904
- 7 - C 20 OR2 ! 0 4 0 1 |DISPLAY:1|:919
- 2 - C 20 AND2 s 0 3 0 1 |DISPLAY:1|~1000~1
- 1 - C 20 OR2 0 4 1 0 |DISPLAY:1|:1050
- 4 - B 17 OR2 0 4 1 0 |DISPLAY:1|:1099
- 1 - B 17 OR2 0 3 0 1 |DISPLAY:1|:1144
- 5 - B 17 OR2 s 0 4 0 1 |DISPLAY:1|~1146~1
- 6 - B 23 OR2 0 3 1 0 |DISPLAY:1|:1150
- 5 - C 20 OR2 0 4 0 1 |DISPLAY:1|:1168
- 3 - C 20 OR2 0 3 0 1 |DISPLAY:1|:1177
- 8 - B 23 OR2 0 4 0 1 |DISPLAY:1|:1194
- 7 - B 23 OR2 0 4 1 0 |DISPLAY:1|:1201
- 4 - C 20 OR2 0 4 1 0 |DISPLAY:1|:1252
- 8 - C 20 OR2 0 4 1 0 |DISPLAY:1|:1303
- 4 - B 23 OR2 s 0 4 0 1 |DISPLAY:1|~1339~1
- 2 - B 23 AND2 s 0 3 0 1 |DISPLAY:1|~1348~1
- 6 - C 20 OR2 0 4 1 0 |DISPLAY:1|:1354
- 3 - D 19 DFFE 0 2 0 1 |REG32B:3|REG3231 (|REG32B:3|:66)
- 3 - D 15 DFFE 0 2 0 1 |REG32B:3|REG3230 (|REG32B:3|:67)
- 3 - D 24 DFFE 0 2 0 1 |REG32B:3|REG3229 (|REG32B:3|:68)
- 3 - D 17 DFFE 0 2 0 1 |REG32B:3|REG3228 (|REG32B:3|:69)
- 4 - D 19 DFFE 0 2 0 1 |REG32B:3|REG3227 (|REG32B:3|:70)
- 5 - D 15 DFFE 0 2 0 1 |REG32B:3|REG3226 (|REG32B:3|:71)
- 4 - D 24 DFFE 0 2 0 1 |REG32B:3|REG3225 (|REG32B:3|:72)
- 5 - D 17 DFFE 0 2 0 1 |REG32B:3|REG3224 (|REG32B:3|:73)
- 2 - D 19 DFFE 0 2 0 1 |REG32B:3|REG3223 (|REG32B:3|:74)
- 2 - D 15 DFFE 0 2 0 1 |REG32B:3|REG3222 (|REG32B:3|:75)
- 2 - D 24 DFFE 0 2 0 1 |REG32B:3|REG3221 (|REG32B:3|:76)
- 2 - D 17 DFFE 0 2 0 1 |REG32B:3|REG3220 (|REG32B:3|:77)
- 7 - D 19 DFFE 0 2 0 1 |REG32B:3|REG3219 (|REG32B:3|:78)
- 8 - D 15 DFFE 0 2 0 1 |REG32B:3|REG3218 (|REG32B:3|:79)
- 8 - D 24 DFFE 0 2 0 1 |REG32B:3|REG3217 (|REG32B:3|:80)
- 8 - D 17 DFFE 0 2 0 1 |REG32B:3|REG3216 (|REG32B:3|:81)
- 2 - E 17 DFFE 0 2 0 1 |REG32B:3|REG3215 (|REG32B:3|:82)
- 2 - E 21 DFFE 0 2 0 1 |REG32B:3|REG3214 (|REG32B:3|:83)
- 1 - E 20 DFFE 0 2 0 1 |REG32B:3|REG3213 (|REG32B:3|:84)
- 2 - E 13 DFFE 0 2 0 1 |REG32B:3|REG3212 (|REG32B:3|:85)
- 4 - E 17 DFFE 0 2 0 1 |REG32B:3|REG3211 (|REG32B:3|:86)
- 4 - E 21 DFFE 0 2 0 1 |REG32B:3|REG3210 (|REG32B:3|:87)
- 4 - E 20 DFFE 0 2 0 1 |REG32B:3|REG329 (|REG32B:3|:88)
- 4 - E 13 DFFE 0 2 0 1 |REG32B:3|REG328 (|REG32B:3|:89)
- 6 - E 17 DFFE 0 2 0 1 |REG32B:3|REG327 (|REG32B:3|:90)
- 6 - E 21 DFFE 0 2 0 1 |REG32B:3|REG326 (|REG32B:3|:91)
- 6 - E 20 DFFE 0 2 0 1 |REG32B:3|REG325 (|REG32B:3|:92)
- 6 - E 13 DFFE 0 2 0 1 |REG32B:3|REG324 (|REG32B:3|:93)
- 8 - E 17 DFFE 0 2 0 1 |REG32B:3|REG323 (|REG32B:3|:94)
- 8 - E 21 DFFE 0 2 0 1 |REG32B:3|REG322 (|REG32B:3|:95)
- 8 - E 20 DFFE 0 2 0 1 |REG32B:3|REG321 (|REG32B:3|:96)
- 8 - E 13 DFFE 0 2 0 1 |REG32B:3|REG320 (|REG32B:3|:97)
- 5 - D 24 DFFE 1 0 0 80 |TESTCTL:5|DIV2CLK (|TESTCTL:5|:5)
- 8 - D 19 OR2 ! 1 1 0 39 |TESTCTL:5|:36
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\eda38\k4\plj\top.rpt
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** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 5/ 96( 5%) 0/ 48( 0%) 6/ 48( 12%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 3/ 96( 3%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
D: 13/ 96( 13%) 1/ 48( 2%) 25/ 48( 52%) 1/16( 6%) 3/16( 18%) 0/16( 0%)
E: 9/ 96( 9%) 0/ 48( 0%) 28/ 48( 58%) 2/16( 12%) 0/16( 0%) 0/16( 0%)
F: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\eda38\k4\plj\top.rpt
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** CLOCK SIGNALS **
Type Fan-out Name
DFF 81 |TESTCTL:5|DIV2CLK
INPUT 13 DISCLK
DFF 6 |COUNT10_8:11|CNT10:U~131|C_sig
DFF 6 |COUNT10_8:11|CNT10:U~114|C_sig
DFF 6 |COUNT10_8:11|CNT10:U~97|C_sig
DFF 6 |COUNT10_8:11|CNT10:U~80|C_sig
DFF 6 |COUNT10_8:11|CNT10:U~56|C_sig
DFF 6 |COUNT10_8:11|CNT10:U|C_sig
DFF 5 |COUNT10_8:11|CNT10:U~148|C_sig
INPUT 5 FSIN
INPUT 2 CLK
Device-Specific Information: f:\eda38\k4\plj\top.rpt
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** CLEAR SIGNALS **
Type Fan-out Name
LCELL 39 |TESTCTL:5|:36
Device-Specific Information: f:\eda38\k4\plj\top.rpt
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** EQUATIONS **
CLK : INPUT;
DISCLK : INPUT;
FSIN : INPUT;
-- Node name is 'L0'
-- Equation name is 'L0', type is output
L0 = _LC6_C20;
-- Node name is 'L1'
-- Equation name is 'L1', type is output
L1 = _LC8_C20;
-- Node name is 'L2'
-- Equation name is 'L2', type is output
L2 = _LC4_C20;
-- Node name is 'L3'
-- Equation name is 'L3', type is output
L3 = _LC7_B23;
-- Node name is 'L4'
-- Equation name is 'L4', type is output
L4 = _LC6_B23;
-- Node name is 'L5'
-- Equation name is 'L5', type is output
L5 = _LC4_B17;
-- Node name is 'L6'
-- Equation name is 'L6', type is output
L6 = _LC1_C20;
-- Node name is 'S20'
-- Equation name is 'S20', type is output
S20 = _LC4_D13;
-- Node name is 'S21'
-- Equation name is 'S21', type is output
S21 = _LC5_D13;
-- Node name is 'S22'
-- Equation name is 'S22', type is output
S22 = _LC5_D14;
-- Node name is '|COUNT10_8:11|CNT10:U|:12' = '|COUNT10_8:11|CNT10:U|cqi0'
-- Equation name is '_LC3_E15', type is buried
_LC3_E15 = DFFE( _EQ001, FSIN, !_LC8_D19, VCC, VCC);
_EQ001 = !_LC3_E15 & _LC5_D24
# _LC3_E15 & !_LC5_D24;
-- Node name is '|COUNT10_8:11|CNT10:U|:11' = '|COUNT10_8:11|CNT10:U|cqi1'
-- Equation name is '_LC7_E15', type is buried
_LC7_E15 = DFFE( _EQ002, FSIN, !_LC8_D19, VCC, VCC);
_EQ002 = !_LC3_E15 & _LC7_E15
# _LC3_E15 & _LC4_E15 & _LC5_D24 & !_LC7_E15
# !_LC5_D24 & _LC7_E15;
-- Node name is '|COUNT10_8:11|CNT10:U|:10' = '|COUNT10_8:11|CNT10:U|cqi2'
-- Equation name is '_LC2_E15', type is buried
_LC2_E15 = DFFE( _EQ003, FSIN, !_LC8_D19, VCC, VCC);
_EQ003 = _LC1_E15 & _LC2_E15 & !_LC6_E15
# _LC1_E15 & !_LC2_E15 & _LC6_E15
# _LC2_E15 & !_LC5_D24;
-- Node name is '|COUNT10_8:11|CNT10:U|:9' = '|COUNT10_8:11|CNT10:U|cqi3'
-- Equation name is '_LC8_E15', type is buried
_LC8_E15 = DFFE( _EQ004, FSIN, !_LC8_D19, VCC, VCC);
_EQ004 = _LC1_E15 & !_LC5_E15 & _LC8_E15
# _LC1_E15 & _LC5_E15 & !_LC8_E15
# !_LC5_D24 & _LC8_E15;
-- Node name is '|COUNT10_8:11|CNT10:U|:13' = '|COUNT10_8:11|CNT10:U|C_sig'
-- Equation name is '_LC1_E22', type is buried
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