📄 top.rpt
字号:
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
B17 5/ 8( 62%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
B23 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 7/22( 31%)
C20 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 4/22( 18%)
D6 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 1/22( 4%)
D13 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 3/22( 13%)
D14 8/ 8(100%) 4/ 8( 50%) 4/ 8( 50%) 1/2 0/2 4/22( 18%)
D15 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 11/22( 50%)
D17 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 11/22( 50%)
D18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
D19 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 1/2 0/2 9/22( 40%)
D20 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
D21 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
D22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 4/22( 18%)
D23 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
D24 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 2/2 0/2 8/22( 36%)
E13 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 11/22( 50%)
E15 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
E16 2/ 8( 25%) 1/ 8( 12%) 2/ 8( 25%) 2/2 0/2 5/22( 22%)
E17 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 11/22( 50%)
E18 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 3/22( 13%)
E19 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
E20 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 11/22( 50%)
E21 8/ 8(100%) 1/ 8( 12%) 0/ 8( 0%) 2/2 0/2 11/22( 50%)
E22 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 2/2 0/2 6/22( 27%)
E23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 0/6 ( 0%)
Total I/O pins used: 13/96 ( 13%)
Total logic cells used: 172/1152 ( 14%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.77/4 ( 69%)
Total fan-in: 478/4608 ( 10%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 10
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 172
Total flipflops required: 85
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 13/1152 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 8 0 13/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 8/0
D: 0 0 0 0 0 8 0 0 0 0 0 0 0 2 8 8 0 8 8 8 8 8 1 8 8 83/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 2 8 8 8 8 8 2 8 0 68/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 8 0 0 0 0 0 0 0 10 8 16 2 21 16 16 24 16 3 24 8 172/0
Device-Specific Information: f:\eda38\k4\plj\top.rpt
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** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
23 - - D -- INPUT 0 0 0 2 CLK
26 - - E -- INPUT 0 0 0 13 DISCLK
27 - - E -- INPUT 0 0 0 5 FSIN
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\eda38\k4\plj\top.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
90 - - C -- OUTPUT 0 1 0 0 L0
91 - - C -- OUTPUT 0 1 0 0 L1
92 - - C -- OUTPUT 0 1 0 0 L2
95 - - B -- OUTPUT 0 1 0 0 L3
96 - - B -- OUTPUT 0 1 0 0 L4
97 - - B -- OUTPUT 0 1 0 0 L5
98 - - B -- OUTPUT 0 1 0 0 L6
20 - - D -- OUTPUT 0 1 0 0 S20
21 - - D -- OUTPUT 0 1 0 0 S21
22 - - D -- OUTPUT 0 1 0 0 S22
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\eda38\k4\plj\top.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - E 15 AND2 0 2 0 1 |COUNT10_8:11|CNT10:U|LPM_ADD_SUB:79|addcore:adder|:55
- 5 - E 15 AND2 0 3 0 1 |COUNT10_8:11|CNT10:U|LPM_ADD_SUB:79|addcore:adder|:59
- 8 - E 15 DFFE 1 4 0 2 |COUNT10_8:11|CNT10:U|cqi3 (|COUNT10_8:11|CNT10:U|:9)
- 2 - E 15 DFFE 1 4 0 3 |COUNT10_8:11|CNT10:U|cqi2 (|COUNT10_8:11|CNT10:U|:10)
- 7 - E 15 DFFE 1 4 0 4 |COUNT10_8:11|CNT10:U|cqi1 (|COUNT10_8:11|CNT10:U|:11)
- 3 - E 15 DFFE 1 2 0 5 |COUNT10_8:11|CNT10:U|cqi0 (|COUNT10_8:11|CNT10:U|:12)
- 1 - E 22 DFFE 1 3 0 5 |COUNT10_8:11|CNT10:U|C_sig (|COUNT10_8:11|CNT10:U|:13)
- 4 - E 15 OR2 s 0 3 0 2 |COUNT10_8:11|CNT10:U|~52~1
- 8 - E 19 AND2 0 2 0 1 |COUNT10_8:11|CNT10:U~56|LPM_ADD_SUB:79|addcore:adder|:55
- 7 - E 19 AND2 0 3 0 1 |COUNT10_8:11|CNT10:U~56|LPM_ADD_SUB:79|addcore:adder|:59
- 4 - E 19 DFFE 0 5 0 2 |COUNT10_8:11|CNT10:U~56|cqi3 (|COUNT10_8:11|CNT10:U~56|:9)
- 2 - E 19 DFFE 0 5 0 3 |COUNT10_8:11|CNT10:U~56|cqi2 (|COUNT10_8:11|CNT10:U~56|:10)
- 5 - E 19 DFFE 0 5 0 4 |COUNT10_8:11|CNT10:U~56|cqi1 (|COUNT10_8:11|CNT10:U~56|:11)
- 3 - E 19 DFFE 0 3 0 5 |COUNT10_8:11|CNT10:U~56|cqi0 (|COUNT10_8:11|CNT10:U~56|:12)
- 4 - E 16 DFFE 0 4 0 5 |COUNT10_8:11|CNT10:U~56|C_sig (|COUNT10_8:11|CNT10:U~56|:13)
- 6 - E 19 OR2 s 0 3 0 2 |COUNT10_8:11|CNT10:U~56|~52~1
- 1 - E 19 OR2 0 3 0 3 |COUNT10_8:11|CNT10:U~56|:165
- 8 - E 23 AND2 0 2 0 1 |COUNT10_8:11|CNT10:U~80|LPM_ADD_SUB:79|addcore:adder|:55
- 7 - E 23 AND2 0 3 0 1 |COUNT10_8:11|CNT10:U~80|LPM_ADD_SUB:79|addcore:adder|:59
- 4 - E 23 DFFE 0 5 0 2 |COUNT10_8:11|CNT10:U~80|cqi3 (|COUNT10_8:11|CNT10:U~80|:9)
- 1 - E 23 DFFE 0 5 0 3 |COUNT10_8:11|CNT10:U~80|cqi2 (|COUNT10_8:11|CNT10:U~80|:10)
- 6 - E 23 DFFE 0 5 0 4 |COUNT10_8:11|CNT10:U~80|cqi1 (|COUNT10_8:11|CNT10:U~80|:11)
- 3 - E 23 DFFE 0 3 0 5 |COUNT10_8:11|CNT10:U~80|cqi0 (|COUNT10_8:11|CNT10:U~80|:12)
- 2 - E 16 DFFE 0 4 0 5 |COUNT10_8:11|CNT10:U~80|C_sig (|COUNT10_8:11|CNT10:U~80|:13)
- 5 - E 23 OR2 s 0 3 0 2 |COUNT10_8:11|CNT10:U~80|~52~1
- 2 - E 23 OR2 0 3 0 3 |COUNT10_8:11|CNT10:U~80|:165
- 8 - E 18 AND2 0 2 0 1 |COUNT10_8:11|CNT10:U~97|LPM_ADD_SUB:79|addcore:adder|:55
- 7 - E 18 AND2 0 3 0 1 |COUNT10_8:11|CNT10:U~97|LPM_ADD_SUB:79|addcore:adder|:59
- 3 - E 18 DFFE 0 5 0 2 |COUNT10_8:11|CNT10:U~97|cqi3 (|COUNT10_8:11|CNT10:U~97|:9)
- 2 - E 18 DFFE 0 5 0 3 |COUNT10_8:11|CNT10:U~97|cqi2 (|COUNT10_8:11|CNT10:U~97|:10)
- 5 - E 18 DFFE 0 5 0 4 |COUNT10_8:11|CNT10:U~97|cqi1 (|COUNT10_8:11|CNT10:U~97|:11)
- 4 - E 18 DFFE 0 3 0 5 |COUNT10_8:11|CNT10:U~97|cqi0 (|COUNT10_8:11|CNT10:U~97|:12)
- 4 - D 15 DFFE 0 4 0 5 |COUNT10_8:11|CNT10:U~97|C_sig (|COUNT10_8:11|CNT10:U~97|:13)
- 6 - E 18 OR2 s 0 3 0 2 |COUNT10_8:11|CNT10:U~97|~52~1
- 1 - E 18 OR2 0 3 0 3 |COUNT10_8:11|CNT10:U~97|:165
- 8 - D 23 AND2 0 2 0 1 |COUNT10_8:11|CNT10:U~114|LPM_ADD_SUB:79|addcore:adder|:55
- 7 - D 23 AND2 0 3 0 1 |COUNT10_8:11|CNT10:U~114|LPM_ADD_SUB:79|addcore:adder|:59
- 4 - D 23 DFFE 0 5 0 2 |COUNT10_8:11|CNT10:U~114|cqi3 (|COUNT10_8:11|CNT10:U~114|:9)
- 1 - D 23 DFFE 0 5 0 3 |COUNT10_8:11|CNT10:U~114|cqi2 (|COUNT10_8:11|CNT10:U~114|:10)
- 3 - D 23 DFFE 0 5 0 4 |COUNT10_8:11|CNT10:U~114|cqi1 (|COUNT10_8:11|CNT10:U~114|:11)
- 5 - D 23 DFFE 0 3 0 5 |COUNT10_8:11|CNT10:U~114|cqi0 (|COUNT10_8:11|CNT10:U~114|:12)
- 2 - E 22 DFFE 0 4 0 5 |COUNT10_8:11|CNT10:U~114|C_sig (|COUNT10_8:11|CNT10:U~114|:13)
- 6 - D 23 OR2 s 0 3 0 2 |COUNT10_8:11|CNT10:U~114|~52~1
- 2 - D 23 OR2 0 3 0 3 |COUNT10_8:11|CNT10:U~114|:165
- 8 - D 20 AND2 0 2 0 1 |COUNT10_8:11|CNT10:U~131|LPM_ADD_SUB:79|addcore:adder|:55
- 7 - D 20 AND2 0 3 0 1 |COUNT10_8:11|CNT10:U~131|LPM_ADD_SUB:79|addcore:adder|:59
- 2 - D 20 DFFE 0 5 0 2 |COUNT10_8:11|CNT10:U~131|cqi3 (|COUNT10_8:11|CNT10:U~131|:9)
- 3 - D 20 DFFE 0 5 0 3 |COUNT10_8:11|CNT10:U~131|cqi2 (|COUNT10_8:11|CNT10:U~131|:10)
- 5 - D 20 DFFE 0 5 0 4 |COUNT10_8:11|CNT10:U~131|cqi1 (|COUNT10_8:11|CNT10:U~131|:11)
- 4 - D 20 DFFE 0 3 0 5 |COUNT10_8:11|CNT10:U~131|cqi0 (|COUNT10_8:11|CNT10:U~131|:12)
- 4 - D 17 DFFE 0 4 0 5 |COUNT10_8:11|CNT10:U~131|C_sig (|COUNT10_8:11|CNT10:U~131|:13)
- 6 - D 20 OR2 s 0 3 0 2 |COUNT10_8:11|CNT10:U~131|~52~1
- 1 - D 20 OR2 0 3 0 3 |COUNT10_8:11|CNT10:U~131|:165
- 8 - D 18 AND2 0 2 0 1 |COUNT10_8:11|CNT10:U~148|LPM_ADD_SUB:79|addcore:adder|:55
- 7 - D 18 AND2 0 3 0 1 |COUNT10_8:11|CNT10:U~148|LPM_ADD_SUB:79|addcore:adder|:59
- 2 - D 18 DFFE 0 5 0 2 |COUNT10_8:11|CNT10:U~148|cqi3 (|COUNT10_8:11|CNT10:U~148|:9)
- 4 - D 18 DFFE 0 5 0 3 |COUNT10_8:11|CNT10:U~148|cqi2 (|COUNT10_8:11|CNT10:U~148|:10)
- 3 - D 18 DFFE 0 5 0 4 |COUNT10_8:11|CNT10:U~148|cqi1 (|COUNT10_8:11|CNT10:U~148|:11)
- 5 - D 18 DFFE 0 3 0 5 |COUNT10_8:11|CNT10:U~148|cqi0 (|COUNT10_8:11|CNT10:U~148|:12)
- 1 - D 22 DFFE 0 4 0 4 |COUNT10_8:11|CNT10:U~148|C_sig (|COUNT10_8:11|CNT10:U~148|:13)
- 6 - D 18 OR2 s 0 3 0 2 |COUNT10_8:11|CNT10:U~148|~52~1
- 1 - D 18 OR2 0 3 0 3 |COUNT10_8:11|CNT10:U~148|:165
- 8 - D 21 AND2 0 2 0 1 |COUNT10_8:11|CNT10:U~165|LPM_ADD_SUB:79|addcore:adder|:55
- 7 - D 21 AND2 0 3 0 1 |COUNT10_8:11|CNT10:U~165|LPM_ADD_SUB:79|addcore:adder|:59
- 3 - D 21 DFFE 0 5 0 2 |COUNT10_8:11|CNT10:U~165|cqi3 (|COUNT10_8:11|CNT10:U~165|:9)
- 1 - D 21 DFFE 0 5 0 3 |COUNT10_8:11|CNT10:U~165|cqi2 (|COUNT10_8:11|CNT10:U~165|:10)
- 2 - D 21 DFFE 0 5 0 4 |COUNT10_8:11|CNT10:U~165|cqi1 (|COUNT10_8:11|CNT10:U~165|:11)
- 4 - D 21 DFFE 0 3 0 5 |COUNT10_8:11|CNT10:U~165|cqi0 (|COUNT10_8:11|CNT10:U~165|:12)
- 5 - D 21 OR2 s 0 3 0 2 |COUNT10_8:11|CNT10:U~165|~52~1
- 6 - D 21 OR2 s 0 3 0 2 |COUNT10_8:11|CNT10:U~165|~153~1
- 1 - E 15 OR2 0 3 0 3 |COUNT10_8:11|CNT10:U|:165
- 1 - D 06 OR2 ! 0 3 0 4 |DISPLAY:1|LPM_ADD_SUB:129|addcore:adder|:67
- 4 - D 06 DFFE 1 3 0 8 |DISPLAY:1|q5 (|DISPLAY:1|:44)
- 2 - D 06 DFFE 1 2 0 10 |DISPLAY:1|q4 (|DISPLAY:1|:45)
- 8 - D 06 DFFE 1 2 0 11 |DISPLAY:1|q3 (|DISPLAY:1|:46)
- 5 - D 06 DFFE 1 3 0 1 |DISPLAY:1|q2 (|DISPLAY:1|:47)
- 7 - D 06 DFFE 1 2 0 2 |DISPLAY:1|q1 (|DISPLAY:1|:48)
- 6 - D 06 DFFE 1 0 0 3 |DISPLAY:1|q0 (|DISPLAY:1|:49)
- 1 - E 17 DFFE 1 3 0 16 |DISPLAY:1|num3~115 (|DISPLAY:1|:53)
- 1 - E 21 DFFE 1 3 0 16 |DISPLAY:1|num2~115 (|DISPLAY:1|:54)
- 2 - E 20 DFFE 1 3 0 16 |DISPLAY:1|num1~115 (|DISPLAY:1|:55)
- 1 - E 13 DFFE 1 3 0 14 |DISPLAY:1|num0 (|DISPLAY:1|:56)
- 5 - D 14 DFFE 1 4 1 0 |DISPLAY:1|sel2 (|DISPLAY:1|:57)
- 5 - D 13 DFFE 1 1 1 0 |DISPLAY:1|sel1 (|DISPLAY:1|:58)
- 4 - D 13 DFFE 1 1 1 0 |DISPLAY:1|sel0 (|DISPLAY:1|:59)
- 3 - D 06 OR2 ! 0 4 0 3 |DISPLAY:1|:92
- 7 - D 14 OR2 ! 0 3 0 5 |DISPLAY:1|:331
- 6 - D 14 OR2 ! 0 3 0 5 |DISPLAY:1|:338
- 3 - D 14 OR2 ! 0 3 0 5 |DISPLAY:1|:345
- 2 - D 14 OR2 ! 0 3 0 5 |DISPLAY:1|:352
- 1 - D 14 AND2 0 3 0 4 |DISPLAY:1|:359
- 4 - D 14 OR2 ! 0 3 0 4 |DISPLAY:1|:366
- 8 - D 14 AND2 0 3 0 4 |DISPLAY:1|:373
- 5 - D 19 OR2 0 3 0 1 |DISPLAY:1|:562
- 6 - D 19 OR2 0 3 0 1 |DISPLAY:1|:568
- 1 - D 19 OR2 0 3 0 1 |DISPLAY:1|:574
- 3 - E 17 OR2 0 3 0 1 |DISPLAY:1|:580
- 5 - E 17 OR2 0 3 0 1 |DISPLAY:1|:586
- 7 - E 17 OR2 0 3 0 1 |DISPLAY:1|:592
- 6 - D 15 OR2 0 3 0 1 |DISPLAY:1|:604
- 7 - D 15 OR2 0 3 0 1 |DISPLAY:1|:607
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