📄 reg32b.rpt
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& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\eda38\k4\plj\reg32b.rpt
reg32b
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
8 - - A -- OUTPUT 0 1 0 0 DOUT0
99 - - A -- OUTPUT 0 1 0 0 DOUT1
21 - - B -- OUTPUT 0 1 0 0 DOUT2
117 - - - 06 OUTPUT 0 1 0 0 DOUT3
91 - - B -- OUTPUT 0 1 0 0 DOUT4
13 - - A -- OUTPUT 0 1 0 0 DOUT5
33 - - C -- OUTPUT 0 1 0 0 DOUT6
30 - - C -- OUTPUT 0 1 0 0 DOUT7
79 - - C -- OUTPUT 0 1 0 0 DOUT8
46 - - - 17 OUTPUT 0 1 0 0 DOUT9
135 - - - 18 OUTPUT 0 1 0 0 DOUT10
90 - - B -- OUTPUT 0 1 0 0 DOUT11
26 - - C -- OUTPUT 0 1 0 0 DOUT12
7 - - A -- OUTPUT 0 1 0 0 DOUT13
82 - - C -- OUTPUT 0 1 0 0 DOUT14
95 - - A -- OUTPUT 0 1 0 0 DOUT15
29 - - C -- OUTPUT 0 1 0 0 DOUT16
17 - - B -- OUTPUT 0 1 0 0 DOUT17
112 - - - 03 OUTPUT 0 1 0 0 DOUT18
88 - - B -- OUTPUT 0 1 0 0 DOUT19
64 - - - 10 OUTPUT 0 1 0 0 DOUT20
101 - - A -- OUTPUT 0 1 0 0 DOUT21
89 - - B -- OUTPUT 0 1 0 0 DOUT22
100 - - A -- OUTPUT 0 1 0 0 DOUT23
28 - - C -- OUTPUT 0 1 0 0 DOUT24
23 - - B -- OUTPUT 0 1 0 0 DOUT25
11 - - A -- OUTPUT 0 1 0 0 DOUT26
92 - - B -- OUTPUT 0 1 0 0 DOUT27
27 - - C -- OUTPUT 0 1 0 0 DOUT28
10 - - A -- OUTPUT 0 1 0 0 DOUT29
98 - - A -- OUTPUT 0 1 0 0 DOUT30
83 - - C -- OUTPUT 0 1 0 0 DOUT31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\eda38\k4\plj\reg32b.rpt
reg32b
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - C 07 DFFE + 1 0 1 0 REG3231 (:66)
- 5 - A 11 DFFE + 1 0 1 0 REG3230 (:67)
- 4 - A 17 DFFE + 1 0 1 0 REG3229 (:68)
- 2 - C 19 DFFE + 1 0 1 0 REG3228 (:69)
- 1 - B 03 DFFE + 1 0 1 0 REG3227 (:70)
- 5 - A 13 DFFE + 1 0 1 0 REG3226 (:71)
- 7 - B 15 DFFE + 1 0 1 0 REG3225 (:72)
- 3 - C 21 DFFE + 1 0 1 0 REG3224 (:73)
- 2 - A 06 DFFE + 1 0 1 0 REG3223 (:74)
- 5 - B 05 DFFE + 1 0 1 0 REG3222 (:75)
- 2 - A 03 DFFE + 1 0 1 0 REG3221 (:76)
- 4 - A 09 DFFE + 1 0 1 0 REG3220 (:77)
- 6 - B 07 DFFE + 1 0 1 0 REG3219 (:78)
- 2 - B 04 DFFE + 1 0 1 0 REG3218 (:79)
- 1 - B 18 DFFE + 1 0 1 0 REG3217 (:80)
- 4 - C 19 DFFE + 1 0 1 0 REG3216 (:81)
- 8 - A 04 DFFE + 1 0 1 0 REG3215 (:82)
- 2 - C 06 DFFE + 1 0 1 0 REG3214 (:83)
- 1 - A 21 DFFE + 1 0 1 0 REG3213 (:84)
- 1 - C 18 DFFE + 1 0 1 0 REG3212 (:85)
- 4 - B 06 DFFE + 1 0 1 0 REG3211 (:86)
- 4 - B 17 DFFE + 1 0 1 0 REG3210 (:87)
- 2 - C 17 DFFE + 1 0 1 0 REG329 (:88)
- 5 - C 03 DFFE + 1 0 1 0 REG328 (:89)
- 5 - C 19 DFFE + 1 0 1 0 REG327 (:90)
- 7 - C 22 DFFE + 1 0 1 0 REG326 (:91)
- 7 - A 19 DFFE + 1 0 1 0 REG325 (:92)
- 2 - B 02 DFFE + 1 0 1 0 REG324 (:93)
- 8 - B 06 DFFE + 1 0 1 0 REG323 (:94)
- 5 - B 17 DFFE + 1 0 1 0 REG322 (:95)
- 4 - A 03 DFFE + 1 0 1 0 REG321 (:96)
- 1 - A 22 DFFE + 1 0 1 0 REG320 (:97)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\eda38\k4\plj\reg32b.rpt
reg32b
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/ 96( 7%) 6/ 48( 12%) 6/ 48( 12%) 6/16( 37%) 10/16( 62%) 0/16( 0%)
B: 8/ 96( 8%) 4/ 48( 8%) 4/ 48( 8%) 6/16( 37%) 8/16( 50%) 0/16( 0%)
C: 9/ 96( 9%) 3/ 48( 6%) 7/ 48( 14%) 5/16( 31%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
18: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
19: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\eda38\k4\plj\reg32b.rpt
reg32b
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 32 LOAD
Device-Specific Information: f:\eda38\k4\plj\reg32b.rpt
reg32b
** EQUATIONS **
DIN0 : INPUT;
DIN1 : INPUT;
DIN2 : INPUT;
DIN3 : INPUT;
DIN4 : INPUT;
DIN5 : INPUT;
DIN6 : INPUT;
DIN7 : INPUT;
DIN8 : INPUT;
DIN9 : INPUT;
DIN10 : INPUT;
DIN11 : INPUT;
DIN12 : INPUT;
DIN13 : INPUT;
DIN14 : INPUT;
DIN15 : INPUT;
DIN16 : INPUT;
DIN17 : INPUT;
DIN18 : INPUT;
DIN19 : INPUT;
DIN20 : INPUT;
DIN21 : INPUT;
DIN22 : INPUT;
DIN23 : INPUT;
DIN24 : INPUT;
DIN25 : INPUT;
DIN26 : INPUT;
DIN27 : INPUT;
DIN28 : INPUT;
DIN29 : INPUT;
DIN30 : INPUT;
DIN31 : INPUT;
LOAD : INPUT;
-- Node name is 'DOUT0'
-- Equation name is 'DOUT0', type is output
DOUT0 = REG320;
-- Node name is 'DOUT1'
-- Equation name is 'DOUT1', type is output
DOUT1 = REG321;
-- Node name is 'DOUT2'
-- Equation name is 'DOUT2', type is output
DOUT2 = REG322;
-- Node name is 'DOUT3'
-- Equation name is 'DOUT3', type is output
DOUT3 = REG323;
-- Node name is 'DOUT4'
-- Equation name is 'DOUT4', type is output
DOUT4 = REG324;
-- Node name is 'DOUT5'
-- Equation name is 'DOUT5', type is output
DOUT5 = REG325;
-- Node name is 'DOUT6'
-- Equation name is 'DOUT6', type is output
DOUT6 = REG326;
-- Node name is 'DOUT7'
-- Equation name is 'DOUT7', type is output
DOUT7 = REG327;
-- Node name is 'DOUT8'
-- Equation name is 'DOUT8', type is output
DOUT8 = REG328;
-- Node name is 'DOUT9'
-- Equation name is 'DOUT9', type is output
DOUT9 = REG329;
-- Node name is 'DOUT10'
-- Equation name is 'DOUT10', type is output
DOUT10 = REG3210;
-- Node name is 'DOUT11'
-- Equation name is 'DOUT11', type is output
DOUT11 = REG3211;
-- Node name is 'DOUT12'
-- Equation name is 'DOUT12', type is output
DOUT12 = REG3212;
-- Node name is 'DOUT13'
-- Equation name is 'DOUT13', type is output
DOUT13 = REG3213;
-- Node name is 'DOUT14'
-- Equation name is 'DOUT14', type is output
DOUT14 = REG3214;
-- Node name is 'DOUT15'
-- Equation name is 'DOUT15', type is output
DOUT15 = REG3215;
-- Node name is 'DOUT16'
-- Equation name is 'DOUT16', type is output
DOUT16 = REG3216;
-- Node name is 'DOUT17'
-- Equation name is 'DOUT17', type is output
DOUT17 = REG3217;
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