📄 reg32b.rpt
字号:
Project Information f:\eda38\k4\plj\reg32b.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/09/2008 22:17:01
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
REG32B
** DEVICE SUMMARY **
Chip/ Input Output Bidir Memory Memory LCs
POF Device Pins Pins Pins Bits % Utilized LCs % Utilized
reg32b EPF10K10TC144-3 33 32 0 0 0 % 32 5 %
User Pins: 33 32 0
Device-Specific Information: f:\eda38\k4\plj\reg32b.rpt
reg32b
***** Logic for device 'reg32b' compiled without errors.
Device: EPF10K10TC144-3
FLEX 10K Configuration Scheme: Passive Serial
Device Options:
User-Supplied Start-Up Clock = OFF
Auto-Restart Configuration on Frame Error = OFF
Release Clears Before Tri-States = OFF
Enable Chip_Wide Reset = OFF
Enable Chip-Wide Output Enable = OFF
Enable INIT_DONE Output = OFF
JTAG User Code = 7f
MultiVolt I/O = OFF
R R R R R R R R R R R R R R R R R
E E E E E E E E E E E E E E E E E
S S S S D S S S G V S S S S S S S D S S S
D E E D D G E E D O V E E D G E N C E E D E E D E V E E O E E E
I R R I I N R R I U C R R I D N R D D D D C R R I R R O R C R R U R R R
N V V N N D V V N T C V V N I D V I I I I I V V N V V U V C V V T V V V
1 E E 2 2 I E E 1 1 I E E 2 N I E N N N N N E E 3 E E T E I E E 1 E E E
6 D D 5 6 O D D 7 0 O D D 8 9 O D T 3 4 2 T D D 1 D D 3 D O D D 8 D D D
--------------------------------------------------------------------------_
/ 144 142 140 138 136 134 132 130 128 126 124 122 120 118 116 114 112 110 |_
/ 143 141 139 137 135 133 131 129 127 125 123 121 119 117 115 113 111 109 |
#TCK | 1 108 | ^DATA0
^CONF_DONE | 2 107 | ^DCLK
^nCEO | 3 106 | ^nCE
#TDO | 4 105 | #TDI
VCCIO | 5 104 | GNDIO
VCCINT | 6 103 | GNDINT
DOUT13 | 7 102 | DIN21
DOUT0 | 8 101 | DOUT21
DIN13 | 9 100 | DOUT23
DOUT29 | 10 99 | DOUT1
DOUT26 | 11 98 | DOUT30
DIN20 | 12 97 | DIN15
DOUT5 | 13 96 | DIN29
DIN30 | 14 95 | DOUT15
GNDIO | 15 94 | VCCIO
GNDINT | 16 93 | VCCINT
DOUT17 | 17 92 | DOUT27
DIN19 | 18 91 | DOUT4
DIN22 | 19 EPF10K10TC144-3 90 | DOUT11
DIN18 | 20 89 | DOUT22
DOUT2 | 21 88 | DOUT19
DIN27 | 22 87 | DIN10
DOUT25 | 23 86 | DIN11
VCCIO | 24 85 | GNDIO
VCCINT | 25 84 | GNDINT
DOUT12 | 26 83 | DOUT31
DOUT28 | 27 82 | DOUT14
DOUT24 | 28 81 | DIN24
DOUT16 | 29 80 | DIN12
DOUT7 | 30 79 | DOUT8
DIN7 | 31 78 | DIN14
DIN8 | 32 77 | ^MSEL0
DOUT6 | 33 76 | ^MSEL1
#TMS | 34 75 | VCCINT
^nSTATUS | 35 74 | ^nCONFIG
RESERVED | 36 73 | RESERVED
| 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 _|
\ 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 |
\---------------------------------------------------------------------------
R R R G D R R R V D R R R G D V V D L D G G R R V R R D R G R R R D V R
E E E N I E E E C O E E E N I C C I O I N N E E C E E O E N E E E I C E
S S S D N S S S C U S S S D N C C N A N D D S S C S S U S D S S S N C S
E E E I 5 E E E I T E E E I 6 I I 0 D 1 I I E E I E E T E I E E E 2 I E
R R R O R R R O 9 R R R O N N N N R R O R R 2 R O R R R 3 O R
V V V V V V V V V T T T T V V V V 0 V V V V V
E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: f:\eda38\k4\plj\reg32b.rpt
reg32b
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A3 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 2/22( 9%)
A4 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
A11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A17 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A19 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
A22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B4 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
B5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B6 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B15 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
B17 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 2/22( 9%)
B18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C6 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C17 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 1/22( 4%)
C18 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C19 3/ 8( 37%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 3/22( 13%)
C21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
C22 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 59/96 ( 61%)
Total logic cells used: 32/576 ( 5%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 1.00/4 ( 25%)
Total fan-in: 32/2304 ( 1%)
Total input pins required: 33
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 32
Total flipflops required: 32
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 0/ 576 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 2 1 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 1 1 0 0 11/0
B: 0 1 1 1 1 2 1 0 0 0 0 0 0 0 0 1 0 2 1 0 0 0 0 0 0 11/0
C: 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 3 0 1 1 0 0 10/0
Total: 0 1 4 2 1 4 2 0 1 0 1 0 0 1 0 1 0 4 2 4 0 2 2 0 0 32/0
Device-Specific Information: f:\eda38\k4\plj\reg32b.rpt
reg32b
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
54 - - - -- INPUT 0 0 0 1 DIN0
56 - - - -- INPUT 0 0 0 1 DIN1
124 - - - -- INPUT 0 0 0 1 DIN2
126 - - - -- INPUT 0 0 0 1 DIN3
125 - - - -- INPUT 0 0 0 1 DIN4
41 - - - 20 INPUT 0 0 0 1 DIN5
51 - - - 13 INPUT 0 0 0 1 DIN6
31 - - C -- INPUT 0 0 0 1 DIN7
32 - - C -- INPUT 0 0 0 1 DIN8
130 - - - 14 INPUT 0 0 0 1 DIN9
87 - - B -- INPUT 0 0 0 1 DIN10
86 - - B -- INPUT 0 0 0 1 DIN11
80 - - C -- INPUT 0 0 0 1 DIN12
9 - - A -- INPUT 0 0 0 1 DIN13
78 - - C -- INPUT 0 0 0 1 DIN14
97 - - A -- INPUT 0 0 0 1 DIN15
144 - - - 24 INPUT 0 0 0 1 DIN16
136 - - - 19 INPUT 0 0 0 1 DIN17
20 - - B -- INPUT 0 0 0 1 DIN18
18 - - B -- INPUT 0 0 0 1 DIN19
12 - - A -- INPUT 0 0 0 1 DIN20
102 - - A -- INPUT 0 0 0 1 DIN21
19 - - B -- INPUT 0 0 0 1 DIN22
70 - - - 05 INPUT 0 0 0 1 DIN23
81 - - C -- INPUT 0 0 0 1 DIN24
141 - - - 22 INPUT 0 0 0 1 DIN25
140 - - - 21 INPUT 0 0 0 1 DIN26
22 - - B -- INPUT 0 0 0 1 DIN27
131 - - - 15 INPUT 0 0 0 1 DIN28
96 - - A -- INPUT 0 0 0 1 DIN29
14 - - A -- INPUT 0 0 0 1 DIN30
120 - - - 09 INPUT 0 0 0 1 DIN31
55 - - - -- INPUT G 0 0 0 0 LOAD
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -