count10_8.vhd

数字频率计是一种用来测试周期性变化信号工作频率的装置。其原理是在规定的单位时间（闸门时间）内

--1位十进制计数器
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_UNSIGNED.all;
ENTITY CNT10 IS
		PORT(CLK,CLR,ENA	: IN STD_LOGIC;
		CQ : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
        CARRY_OUT : OUT STD_LOGIC);
END CNT10;
ARCHITECTURE one OF CNT10 IS
    SIGNAL  cqi: STD_LOGIC_VECTOR (3 DOWNTO 0);
    SIGNAL  C_sig: STD_LOGIC;
	BEGIN
        cq<=cqi;
      PROCESS(CLK,CLR,ENA)
    BEGIN
      IF (CLR='1') then cqi<="0000";
      ELSIF( CLK'EVENT AND CLK='1') then
       IF (ENA='1')THEN 
        IF(cqi="1001") then cqi<="0000";
            C_sig<='0';
            ELSE cqi <= cqi+'1';C_sig<='1';
      END if;
     END if;
    END if;
     CARRY_OUT<=C_sig;
   END PROCESS;  
END one;
--用生成语句构成8位十进制计数器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.std_logic_UNSIGNED.all;
ENTITY COUNT10_8 IS    
PORT (CLK:IN STD_LOGIC;    	--计数时钟信号
      CLR:IN STD_LOGIC;    	--清零信号         
      ENA:IN STD_LOGIC;		--计数使能信号
      Q:OUT STD_LOGIC_VECTOR (31 DOWNTO 0);--32位计数结果输出 
CARRY_OUT:OUT STD_LOGIC);    	--计数进位
END ENTITY COUNT10_8;
ARCHITECTURE ART1 OF COUNT10_8 IS 
COMPONENT CNT10 IS --待调用的有时钟使能的十进制计数器端口定义  
 PORT(CLK,CLR,ENA:IN STD_LOGIC;         
      CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);         
      CARRY_OUT:OUT STD_LOGIC);
END COMPONENT CNT10;
SIGNAL  C : STD_LOGIC_VECTOR(8 DOWNTO 0);
BEGIN
  C(0)<=CLK;
bls_1:FOR i IN 0 TO 7 GENERATE
U: CNT10  PORT MAP(C(i), CLR, ENA, Q(4*i+3 DOWNTO 4*i), c(i+1));
END GENERATE bls_1;
 CARRY_OUT<=C(8);
END ART1;