testctl.vhd

来自「数字频率计是一种用来测试周期性变化信号工作频率的装置。其原理是在规定的单位时间（」· VHDL 代码 · 共 29 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY TESTCTL IS
   PORT(CLK:IN STD_LOGIC;
        TSTEN:OUT STD_LOGIC;
        CLR_CNT:OUT STD_LOGIC;
           LOAD:OUT STD_LOGIC);
END TESTCTL;
ARCHITECTURE BEHAVE OF TESTCTL IS
 SIGNAL DIV2CLK:STD_LOGIC;
BEGIN 
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN DIV2CLK<=NOT DIV2CLK;
END IF;
END PROCESS;
PROCESS(CLK,DIV2CLK)
BEGIN
IF CLK='0' AND DIV2CLK='0' THEN
CLR_CNT<='1';----产生计数器清零位
ELSE CLR_CNT<='0';
END IF;
END PROCESS;
LOAD<=NOT(DIV2CLK);
TSTEN<=DIV2CLK;
END BEHAVE;