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📄 ebit_ten_counter.rpt

📁 数字频率计是一种用来测试周期性变化信号工作频率的装置。其原理是在规定的单位时间(闸门时间)内
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_LC3_C4  = DFFE( _EQ029,  _LC5_C4, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ029 =  _LC3_C4 & !_LC8_C4
         #  _LC1_C4 & !_LC3_C4 &  _LC4_C4 &  _LC8_C4
         # !_LC1_C4 &  _LC3_C4 &  _LC4_C4
         #  _LC1_C4 &  _LC3_C4 & !_LC4_C4;

-- Node name is '|ten_counter:u5|:4' 
-- Equation name is '_LC4_C4', type is buried 
_LC4_C4  = DFFE( _EQ030,  _LC5_C4, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ030 = !_LC1_C4 &  _LC4_C4
         #  _LC4_C4 & !_LC8_C4
         #  _LC1_C4 & !_LC4_C4 &  _LC8_C4;

-- Node name is '|ten_counter:u5|:6' 
-- Equation name is '_LC1_C4', type is buried 
_LC1_C4  = DFFE( _EQ031,  _LC5_C4, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ031 =  _LC1_C4 & !_LC6_C4 & !_LC7_C4 & !_LC8_C4
         # !_LC1_C4 & !_LC6_C4 & !_LC7_C4 &  _LC8_C4;

-- Node name is '|ten_counter:u5|:8' 
-- Equation name is '_LC8_C4', type is buried 
_LC8_C4  = DFFE(!_LC8_C4,  _LC5_C4, GLOBAL(!clr_ent),  VCC,  VCC);

-- Node name is '|ten_counter:u5|:12' 
-- Equation name is '_LC2_C4', type is buried 
_LC2_C4  = DFFE( _EQ032,  _LC5_C4,  VCC,  VCC, !_LC1_B9);
  _EQ032 =  _LC2_C4 & !_LC6_C4
         # !_LC6_C4 &  _LC7_C4;

-- Node name is '|ten_counter:u5|:20' 
-- Equation name is '_LC5_C4', type is buried 
_LC5_C4  = LCELL( _EQ033);
  _EQ033 =  cnt_en &  _LC2_C19;

-- Node name is '|ten_counter:u5|:66' 
-- Equation name is '_LC6_C4', type is buried 
!_LC6_C4 = _LC6_C4~NOT;
_LC6_C4~NOT = LCELL( _EQ034);
  _EQ034 =  _LC8_C4
         #  _LC1_C4
         # !_LC3_C4
         #  _LC4_C4;

-- Node name is '|ten_counter:u5|:75' 
-- Equation name is '_LC7_C4', type is buried 
_LC7_C4  = LCELL( _EQ035);
  _EQ035 = !_LC1_C4 &  _LC3_C4 & !_LC4_C4 &  _LC8_C4;

-- Node name is '|ten_counter:u6|:2' 
-- Equation name is '_LC2_B6', type is buried 
_LC2_B6  = DFFE( _EQ036,  _LC5_B6, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ036 = !_LC1_B6 &  _LC2_B6
         #  _LC1_B6 & !_LC2_B6 &  _LC4_B6 &  _LC6_B6
         #  _LC2_B6 & !_LC4_B6 &  _LC6_B6
         #  _LC2_B6 &  _LC4_B6 & !_LC6_B6;

-- Node name is '|ten_counter:u6|:4' 
-- Equation name is '_LC6_B6', type is buried 
_LC6_B6  = DFFE( _EQ037,  _LC5_B6, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ037 = !_LC4_B6 &  _LC6_B6
         # !_LC1_B6 &  _LC6_B6
         #  _LC1_B6 &  _LC4_B6 & !_LC6_B6;

-- Node name is '|ten_counter:u6|:6' 
-- Equation name is '_LC4_B6', type is buried 
_LC4_B6  = DFFE( _EQ038,  _LC5_B6, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ038 = !_LC1_B6 &  _LC4_B6 & !_LC7_B6 & !_LC8_B6
         #  _LC1_B6 & !_LC4_B6 & !_LC7_B6 & !_LC8_B6;

-- Node name is '|ten_counter:u6|:8' 
-- Equation name is '_LC1_B6', type is buried 
_LC1_B6  = DFFE(!_LC1_B6,  _LC5_B6, GLOBAL(!clr_ent),  VCC,  VCC);

-- Node name is '|ten_counter:u6|:12' 
-- Equation name is '_LC3_B6', type is buried 
_LC3_B6  = DFFE( _EQ039,  _LC5_B6,  VCC,  VCC, !_LC1_B9);
  _EQ039 =  _LC3_B6 & !_LC7_B6
         # !_LC7_B6 &  _LC8_B6;

-- Node name is '|ten_counter:u6|:20' 
-- Equation name is '_LC5_B6', type is buried 
_LC5_B6  = LCELL( _EQ040);
  _EQ040 =  cnt_en &  _LC2_C4;

-- Node name is '|ten_counter:u6|:66' 
-- Equation name is '_LC7_B6', type is buried 
!_LC7_B6 = _LC7_B6~NOT;
_LC7_B6~NOT = LCELL( _EQ041);
  _EQ041 =  _LC1_B6
         #  _LC4_B6
         # !_LC2_B6
         #  _LC6_B6;

-- Node name is '|ten_counter:u6|:75' 
-- Equation name is '_LC8_B6', type is buried 
_LC8_B6  = LCELL( _EQ042);
  _EQ042 =  _LC1_B6 &  _LC2_B6 & !_LC4_B6 & !_LC6_B6;

-- Node name is '|ten_counter:u7|:2' 
-- Equation name is '_LC8_B2', type is buried 
_LC8_B2  = DFFE( _EQ043,  _LC2_B2, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ043 = !_LC5_B2 &  _LC8_B2
         #  _LC4_B2 &  _LC5_B2 &  _LC6_B2 & !_LC8_B2
         # !_LC4_B2 &  _LC6_B2 &  _LC8_B2
         #  _LC4_B2 & !_LC6_B2 &  _LC8_B2;

-- Node name is '|ten_counter:u7|:4' 
-- Equation name is '_LC6_B2', type is buried 
_LC6_B2  = DFFE( _EQ044,  _LC2_B2, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ044 = !_LC4_B2 &  _LC6_B2
         # !_LC5_B2 &  _LC6_B2
         #  _LC4_B2 &  _LC5_B2 & !_LC6_B2;

-- Node name is '|ten_counter:u7|:6' 
-- Equation name is '_LC4_B2', type is buried 
_LC4_B2  = DFFE( _EQ045,  _LC2_B2, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ045 = !_LC3_B2 &  _LC4_B2 & !_LC5_B2 & !_LC7_B2
         # !_LC3_B2 & !_LC4_B2 &  _LC5_B2 & !_LC7_B2;

-- Node name is '|ten_counter:u7|:8' 
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = DFFE(!_LC5_B2,  _LC2_B2, GLOBAL(!clr_ent),  VCC,  VCC);

-- Node name is '|ten_counter:u7|:12' 
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = DFFE( _EQ046,  _LC2_B2,  VCC,  VCC, !_LC1_B9);
  _EQ046 =  _LC1_B2 & !_LC3_B2
         # !_LC3_B2 &  _LC7_B2;

-- Node name is '|ten_counter:u7|:20' 
-- Equation name is '_LC2_B2', type is buried 
_LC2_B2  = LCELL( _EQ047);
  _EQ047 =  cnt_en &  _LC3_B6;

-- Node name is '|ten_counter:u7|:66' 
-- Equation name is '_LC3_B2', type is buried 
!_LC3_B2 = _LC3_B2~NOT;
_LC3_B2~NOT = LCELL( _EQ048);
  _EQ048 =  _LC5_B2
         #  _LC4_B2
         # !_LC8_B2
         #  _LC6_B2;

-- Node name is '|ten_counter:u7|:75' 
-- Equation name is '_LC7_B2', type is buried 
_LC7_B2  = LCELL( _EQ049);
  _EQ049 = !_LC4_B2 &  _LC5_B2 & !_LC6_B2 &  _LC8_B2;

-- Node name is '|ten_counter:u8|:2' 
-- Equation name is '_LC8_B8', type is buried 
_LC8_B8  = DFFE( _EQ050,  _LC3_B8, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ050 =  _LC2_B8 &  _LC5_B8 &  _LC6_B8 & !_LC8_B8
         # !_LC6_B8 &  _LC8_B8
         #  _LC2_B8 & !_LC5_B8 &  _LC8_B8
         # !_LC2_B8 &  _LC5_B8 &  _LC8_B8;

-- Node name is '|ten_counter:u8|:4' 
-- Equation name is '_LC2_B8', type is buried 
_LC2_B8  = DFFE( _EQ051,  _LC3_B8, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ051 =  _LC2_B8 & !_LC5_B8
         #  _LC2_B8 & !_LC6_B8
         # !_LC2_B8 &  _LC5_B8 &  _LC6_B8;

-- Node name is '|ten_counter:u8|:6' 
-- Equation name is '_LC5_B8', type is buried 
_LC5_B8  = DFFE( _EQ052,  _LC3_B8, GLOBAL(!clr_ent),  VCC,  VCC);
  _EQ052 = !_LC4_B8 &  _LC5_B8 & !_LC6_B8 & !_LC7_B8
         # !_LC4_B8 & !_LC5_B8 &  _LC6_B8 & !_LC7_B8;

-- Node name is '|ten_counter:u8|:8' 
-- Equation name is '_LC6_B8', type is buried 
_LC6_B8  = DFFE(!_LC6_B8,  _LC3_B8, GLOBAL(!clr_ent),  VCC,  VCC);

-- Node name is '|ten_counter:u8|:12' 
-- Equation name is '_LC1_B8', type is buried 
_LC1_B8  = DFFE( _EQ053,  _LC3_B8,  VCC,  VCC, !_LC1_B9);
  _EQ053 =  _LC1_B8 & !_LC4_B8
         # !_LC4_B8 &  _LC7_B8;

-- Node name is '|ten_counter:u8|:20' 
-- Equation name is '_LC3_B8', type is buried 
_LC3_B8  = LCELL( _EQ054);
  _EQ054 =  cnt_en &  _LC1_B2;

-- Node name is '|ten_counter:u8|:66' 
-- Equation name is '_LC4_B8', type is buried 
!_LC4_B8 = _LC4_B8~NOT;
_LC4_B8~NOT = LCELL( _EQ055);
  _EQ055 =  _LC6_B8
         #  _LC5_B8
         # !_LC8_B8
         #  _LC2_B8;

-- Node name is '|ten_counter:u8|:75' 
-- Equation name is '_LC7_B8', type is buried 
_LC7_B8  = LCELL( _EQ056);
  _EQ056 = !_LC2_B8 & !_LC5_B8 &  _LC6_B8 &  _LC8_B8;



Project Information                       f:\eda38\k4\plj\ebit_ten_counter.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,177K

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