📄 ebit_ten_counter.rpt
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** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
44 - - - -- INPUT 0 0 0 1 clk_test
2 - - - -- INPUT G 0 0 0 1 clr_ent
42 - - - -- INPUT 0 0 0 8 cnt_en
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\eda38\k4\plj\ebit_ten_counter.rpt
ebit_ten_counter
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
19 - - A -- OUTPUT 0 1 0 0 b_bcd0
17 - - A -- OUTPUT 0 1 0 0 b_bcd1
18 - - A -- OUTPUT 0 1 0 0 b_bcd2
16 - - A -- OUTPUT 0 1 0 0 b_bcd3
71 - - A -- OUTPUT 0 1 0 0 bcd0
70 - - A -- OUTPUT 0 1 0 0 bcd1
69 - - A -- OUTPUT 0 1 0 0 bcd2
72 - - A -- OUTPUT 0 1 0 0 bcd3
21 - - B -- OUTPUT 0 1 0 0 c_bcd0
3 - - - 12 OUTPUT 0 1 0 0 c_bcd1
30 - - C -- OUTPUT 0 1 0 0 c_bcd2
39 - - - 11 OUTPUT 0 1 0 0 c_bcd3
58 - - C -- OUTPUT 0 1 0 0 d_bcd0
61 - - C -- OUTPUT 0 1 0 0 d_bcd1
62 - - C -- OUTPUT 0 1 0 0 d_bcd2
60 - - C -- OUTPUT 0 1 0 0 d_bcd3
29 - - C -- OUTPUT 0 1 0 0 e_bcd0
27 - - C -- OUTPUT 0 1 0 0 e_bcd1
7 - - - 03 OUTPUT 0 1 0 0 e_bcd2
6 - - - 04 OUTPUT 0 1 0 0 e_bcd3
35 - - - 06 OUTPUT 0 1 0 0 f_bcd0
23 - - B -- OUTPUT 0 1 0 0 f_bcd1
5 - - - 05 OUTPUT 0 1 0 0 f_bcd2
28 - - C -- OUTPUT 0 1 0 0 f_bcd3
10 - - - 01 OUTPUT 0 1 0 0 g_bcd0
9 - - - 02 OUTPUT 0 1 0 0 g_bcd1
24 - - B -- OUTPUT 0 1 0 0 g_bcd2
65 - - B -- OUTPUT 0 1 0 0 g_bcd3
64 - - B -- OUTPUT 0 1 0 0 h_bcd0
36 - - - 07 OUTPUT 0 1 0 0 h_bcd1
66 - - B -- OUTPUT 0 1 0 0 h_bcd2
25 - - B -- OUTPUT 0 1 0 0 h_bcd3
22 - - B -- OUTPUT 0 1 0 0 sco
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\eda38\k4\plj\ebit_ten_counter.rpt
ebit_ten_counter
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 09 SOFT s ! 1 0 0 8 clr_ent~1
- 2 - A 20 DFFE 0 4 1 2 |ten_counter:u1|:2
- 7 - A 20 DFFE 0 3 1 3 |ten_counter:u1|:4
- 8 - A 20 DFFE 0 4 1 4 |ten_counter:u1|:6
- 4 - A 20 DFFE 0 1 1 5 |ten_counter:u1|:8
- 1 - A 20 DFFE 0 4 0 1 |ten_counter:u1|:12
- 3 - A 20 AND2 2 0 0 5 |ten_counter:u1|:20
- 5 - A 20 OR2 ! 0 4 0 2 |ten_counter:u1|:66
- 6 - A 20 AND2 0 4 0 2 |ten_counter:u1|:75
- 1 - A 03 DFFE 0 4 1 2 |ten_counter:u2|:2
- 5 - A 03 DFFE 0 3 1 3 |ten_counter:u2|:4
- 3 - A 03 DFFE 0 4 1 4 |ten_counter:u2|:6
- 7 - A 03 DFFE 0 1 1 5 |ten_counter:u2|:8
- 2 - A 03 DFFE 0 4 0 1 |ten_counter:u2|:12
- 4 - A 03 AND2 1 1 0 5 |ten_counter:u2|:20
- 6 - A 03 OR2 ! 0 4 0 2 |ten_counter:u2|:66
- 8 - A 03 AND2 0 4 0 2 |ten_counter:u2|:75
- 2 - C 12 DFFE 0 4 1 2 |ten_counter:u3|:2
- 7 - C 12 DFFE 0 3 1 3 |ten_counter:u3|:4
- 3 - C 12 DFFE 0 4 1 4 |ten_counter:u3|:6
- 1 - C 12 DFFE 0 1 1 5 |ten_counter:u3|:8
- 4 - C 12 DFFE 0 4 0 1 |ten_counter:u3|:12
- 5 - C 12 AND2 1 1 0 5 |ten_counter:u3|:20
- 6 - C 12 OR2 ! 0 4 0 2 |ten_counter:u3|:66
- 8 - C 12 AND2 0 4 0 2 |ten_counter:u3|:75
- 4 - C 19 DFFE 0 4 1 2 |ten_counter:u4|:2
- 1 - C 19 DFFE 0 3 1 3 |ten_counter:u4|:4
- 3 - C 19 DFFE 0 4 1 4 |ten_counter:u4|:6
- 7 - C 19 DFFE 0 1 1 5 |ten_counter:u4|:8
- 2 - C 19 DFFE 0 4 0 1 |ten_counter:u4|:12
- 5 - C 19 AND2 1 1 0 5 |ten_counter:u4|:20
- 6 - C 19 OR2 ! 0 4 0 2 |ten_counter:u4|:66
- 8 - C 19 AND2 0 4 0 2 |ten_counter:u4|:75
- 3 - C 04 DFFE 0 4 1 2 |ten_counter:u5|:2
- 4 - C 04 DFFE 0 3 1 3 |ten_counter:u5|:4
- 1 - C 04 DFFE 0 4 1 4 |ten_counter:u5|:6
- 8 - C 04 DFFE 0 1 1 5 |ten_counter:u5|:8
- 2 - C 04 DFFE 0 4 0 1 |ten_counter:u5|:12
- 5 - C 04 AND2 1 1 0 5 |ten_counter:u5|:20
- 6 - C 04 OR2 ! 0 4 0 2 |ten_counter:u5|:66
- 7 - C 04 AND2 0 4 0 2 |ten_counter:u5|:75
- 2 - B 06 DFFE 0 4 1 2 |ten_counter:u6|:2
- 6 - B 06 DFFE 0 3 1 3 |ten_counter:u6|:4
- 4 - B 06 DFFE 0 4 1 4 |ten_counter:u6|:6
- 1 - B 06 DFFE 0 1 1 5 |ten_counter:u6|:8
- 3 - B 06 DFFE 0 4 0 1 |ten_counter:u6|:12
- 5 - B 06 AND2 1 1 0 5 |ten_counter:u6|:20
- 7 - B 06 OR2 ! 0 4 0 2 |ten_counter:u6|:66
- 8 - B 06 AND2 0 4 0 2 |ten_counter:u6|:75
- 8 - B 02 DFFE 0 4 1 2 |ten_counter:u7|:2
- 6 - B 02 DFFE 0 3 1 3 |ten_counter:u7|:4
- 4 - B 02 DFFE 0 4 1 4 |ten_counter:u7|:6
- 5 - B 02 DFFE 0 1 1 5 |ten_counter:u7|:8
- 1 - B 02 DFFE 0 4 0 1 |ten_counter:u7|:12
- 2 - B 02 AND2 1 1 0 5 |ten_counter:u7|:20
- 3 - B 02 OR2 ! 0 4 0 2 |ten_counter:u7|:66
- 7 - B 02 AND2 0 4 0 2 |ten_counter:u7|:75
- 8 - B 08 DFFE 0 4 1 2 |ten_counter:u8|:2
- 2 - B 08 DFFE 0 3 1 3 |ten_counter:u8|:4
- 5 - B 08 DFFE 0 4 1 4 |ten_counter:u8|:6
- 6 - B 08 DFFE 0 1 1 5 |ten_counter:u8|:8
- 1 - B 08 DFFE 0 4 1 0 |ten_counter:u8|:12
- 3 - B 08 AND2 1 1 0 5 |ten_counter:u8|:20
- 4 - B 08 OR2 ! 0 4 0 2 |ten_counter:u8|:66
- 7 - B 08 AND2 0 4 0 2 |ten_counter:u8|:75
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\eda38\k4\plj\ebit_ten_counter.rpt
ebit_ten_counter
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 3/ 48( 6%) 4/ 48( 8%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 5/ 96( 5%) 7/ 48( 14%) 0/ 48( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 4/ 96( 4%) 4/ 48( 8%) 4/ 48( 8%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\eda38\k4\plj\ebit_ten_counter.rpt
ebit_ten_counter
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 5 |ten_counter:u1|:20
LCELL 5 |ten_counter:u2|:20
LCELL 5 |ten_counter:u3|:20
LCELL 5 |ten_counter:u4|:20
LCELL 5 |ten_counter:u5|:20
LCELL 5 |ten_counter:u6|:20
LCELL 5 |ten_counter:u7|:20
LCELL 5 |ten_counter:u8|:20
Device-Specific Information: f:\eda38\k4\plj\ebit_ten_counter.rpt
ebit_ten_counter
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 33 clr_ent
Device-Specific Information: f:\eda38\k4\plj\ebit_ten_counter.rpt
ebit_ten_counter
** EQUATIONS **
clk_test : INPUT;
clr_ent : INPUT;
cnt_en : INPUT;
-- Node name is 'b_bcd0'
-- Equation name is 'b_bcd0', type is output
b_bcd0 = _LC7_A3;
-- Node name is 'b_bcd1'
-- Equation name is 'b_bcd1', type is output
b_bcd1 = _LC3_A3;
-- Node name is 'b_bcd2'
-- Equation name is 'b_bcd2', type is output
b_bcd2 = _LC5_A3;
-- Node name is 'b_bcd3'
-- Equation name is 'b_bcd3', type is output
b_bcd3 = _LC1_A3;
-- Node name is 'bcd0'
-- Equation name is 'bcd0', type is output
bcd0 = _LC4_A20;
-- Node name is 'bcd1'
-- Equation name is 'bcd1', type is output
bcd1 = _LC8_A20;
-- Node name is 'bcd2'
-- Equation name is 'bcd2', type is output
bcd2 = _LC7_A20;
-- Node name is 'bcd3'
-- Equation name is 'bcd3', type is output
bcd3 = _LC2_A20;
-- Node name is 'c_bcd0'
-- Equation name is 'c_bcd0', type is output
c_bcd0 = _LC1_C12;
-- Node name is 'c_bcd1'
-- Equation name is 'c_bcd1', type is output
c_bcd1 = _LC3_C12;
-- Node name is 'c_bcd2'
-- Equation name is 'c_bcd2', type is output
c_bcd2 = _LC7_C12;
-- Node name is 'c_bcd3'
-- Equation name is 'c_bcd3', type is output
c_bcd3 = _LC2_C12;
-- Node name is 'clr_ent~1'
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