📄 count10_8.rpt
字号:
37 - - - 09 OUTPUT 0 1 0 0 Q3
21 - - B -- OUTPUT 0 1 0 0 Q4
66 - - B -- OUTPUT 0 1 0 0 Q5
25 - - B -- OUTPUT 0 1 0 0 Q6
64 - - B -- OUTPUT 0 1 0 0 Q7
7 - - - 03 OUTPUT 0 1 0 0 Q8
8 - - - 03 OUTPUT 0 1 0 0 Q9
6 - - - 04 OUTPUT 0 1 0 0 Q10
29 - - C -- OUTPUT 0 1 0 0 Q11
24 - - B -- OUTPUT 0 1 0 0 Q12
23 - - B -- OUTPUT 0 1 0 0 Q13
65 - - B -- OUTPUT 0 1 0 0 Q14
35 - - - 06 OUTPUT 0 1 0 0 Q15
59 - - C -- OUTPUT 0 1 0 0 Q16
58 - - C -- OUTPUT 0 1 0 0 Q17
62 - - C -- OUTPUT 0 1 0 0 Q18
60 - - C -- OUTPUT 0 1 0 0 Q19
17 - - A -- OUTPUT 0 1 0 0 Q20
18 - - A -- OUTPUT 0 1 0 0 Q21
73 - - A -- OUTPUT 0 1 0 0 Q22
83 - - - 13 OUTPUT 0 1 0 0 Q23
52 - - - 19 OUTPUT 0 1 0 0 Q24
53 - - - 20 OUTPUT 0 1 0 0 Q25
70 - - A -- OUTPUT 0 1 0 0 Q26
71 - - A -- OUTPUT 0 1 0 0 Q27
19 - - A -- OUTPUT 0 1 0 0 Q28
72 - - A -- OUTPUT 0 1 0 0 Q29
69 - - A -- OUTPUT 0 1 0 0 Q30
54 - - - 21 OUTPUT 0 1 0 0 Q31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\eda38\k4\plj\count10_8.rpt
count10_8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 13 SOFT s ! 1 0 0 8 CLR~1
- 8 - B 10 AND2 0 3 0 1 |CNT10:U|LPM_ADD_SUB:79|addcore:adder|:59
- 7 - B 10 OR2 0 3 0 1 |CNT10:U|LPM_ADD_SUB:79|addcore:adder|:68
- 4 - B 10 DFFE + 1 2 1 1 |CNT10:U|cqi3 (|CNT10:U|:9)
- 1 - B 10 DFFE + 1 2 1 3 |CNT10:U|cqi2 (|CNT10:U|:10)
- 2 - B 10 DFFE + 1 2 1 3 |CNT10:U|cqi1 (|CNT10:U|:11)
- 6 - B 10 DFFE + 1 0 1 4 |CNT10:U|cqi0 (|CNT10:U|:12)
- 2 - B 01 DFFE + 1 2 0 5 |CNT10:U|C_sig (|CNT10:U|:13)
- 5 - B 10 OR2 ! 0 4 0 4 |CNT10:U|:52
- 5 - B 01 AND2 0 3 0 1 |CNT10:U~56|LPM_ADD_SUB:79|addcore:adder|:59
- 4 - B 01 OR2 0 3 0 1 |CNT10:U~56|LPM_ADD_SUB:79|addcore:adder|:68
- 7 - B 01 DFFE 1 3 1 1 |CNT10:U~56|cqi3 (|CNT10:U~56|:9)
- 8 - B 01 DFFE 1 3 1 3 |CNT10:U~56|cqi2 (|CNT10:U~56|:10)
- 3 - B 01 DFFE 1 3 1 3 |CNT10:U~56|cqi1 (|CNT10:U~56|:11)
- 1 - B 01 DFFE 1 1 1 4 |CNT10:U~56|cqi0 (|CNT10:U~56|:12)
- 2 - B 03 DFFE 1 3 0 5 |CNT10:U~56|C_sig (|CNT10:U~56|:13)
- 6 - B 01 OR2 ! 0 4 0 4 |CNT10:U~56|:52
- 8 - B 03 AND2 0 3 0 1 |CNT10:U~80|LPM_ADD_SUB:79|addcore:adder|:59
- 3 - B 03 OR2 0 3 0 1 |CNT10:U~80|LPM_ADD_SUB:79|addcore:adder|:68
- 5 - B 03 DFFE 1 3 1 1 |CNT10:U~80|cqi3 (|CNT10:U~80|:9)
- 6 - B 03 DFFE 1 3 1 3 |CNT10:U~80|cqi2 (|CNT10:U~80|:10)
- 7 - B 03 DFFE 1 3 1 3 |CNT10:U~80|cqi1 (|CNT10:U~80|:11)
- 1 - B 03 DFFE 1 1 1 4 |CNT10:U~80|cqi0 (|CNT10:U~80|:12)
- 7 - B 05 DFFE 1 3 0 5 |CNT10:U~80|C_sig (|CNT10:U~80|:13)
- 4 - B 03 OR2 ! 0 4 0 4 |CNT10:U~80|:52
- 8 - B 05 AND2 0 3 0 1 |CNT10:U~97|LPM_ADD_SUB:79|addcore:adder|:59
- 2 - B 05 OR2 0 3 0 1 |CNT10:U~97|LPM_ADD_SUB:79|addcore:adder|:68
- 1 - B 05 DFFE 1 3 1 1 |CNT10:U~97|cqi3 (|CNT10:U~97|:9)
- 5 - B 05 DFFE 1 3 1 3 |CNT10:U~97|cqi2 (|CNT10:U~97|:10)
- 4 - B 05 DFFE 1 3 1 3 |CNT10:U~97|cqi1 (|CNT10:U~97|:11)
- 6 - B 05 DFFE 1 1 1 4 |CNT10:U~97|cqi0 (|CNT10:U~97|:12)
- 3 - B 10 DFFE 1 3 0 5 |CNT10:U~97|C_sig (|CNT10:U~97|:13)
- 3 - B 05 OR2 ! 0 4 0 4 |CNT10:U~97|:52
- 8 - C 17 AND2 0 3 0 1 |CNT10:U~114|LPM_ADD_SUB:79|addcore:adder|:59
- 6 - C 17 OR2 0 3 0 1 |CNT10:U~114|LPM_ADD_SUB:79|addcore:adder|:68
- 4 - C 17 DFFE 1 3 1 1 |CNT10:U~114|cqi3 (|CNT10:U~114|:9)
- 1 - C 17 DFFE 1 3 1 3 |CNT10:U~114|cqi2 (|CNT10:U~114|:10)
- 7 - C 17 DFFE 1 3 1 3 |CNT10:U~114|cqi1 (|CNT10:U~114|:11)
- 5 - C 17 DFFE 1 1 1 4 |CNT10:U~114|cqi0 (|CNT10:U~114|:12)
- 3 - C 17 DFFE 1 3 0 5 |CNT10:U~114|C_sig (|CNT10:U~114|:13)
- 2 - C 17 OR2 ! 0 4 0 4 |CNT10:U~114|:52
- 8 - A 14 AND2 0 3 0 1 |CNT10:U~131|LPM_ADD_SUB:79|addcore:adder|:59
- 7 - A 14 OR2 0 3 0 1 |CNT10:U~131|LPM_ADD_SUB:79|addcore:adder|:68
- 6 - A 14 DFFE 1 3 1 1 |CNT10:U~131|cqi3 (|CNT10:U~131|:9)
- 1 - A 14 DFFE 1 3 1 3 |CNT10:U~131|cqi2 (|CNT10:U~131|:10)
- 5 - A 14 DFFE 1 3 1 3 |CNT10:U~131|cqi1 (|CNT10:U~131|:11)
- 2 - A 14 DFFE 1 1 1 4 |CNT10:U~131|cqi0 (|CNT10:U~131|:12)
- 3 - A 14 DFFE 1 3 0 5 |CNT10:U~131|C_sig (|CNT10:U~131|:13)
- 4 - A 14 OR2 ! 0 4 0 4 |CNT10:U~131|:52
- 8 - A 19 AND2 0 3 0 1 |CNT10:U~148|LPM_ADD_SUB:79|addcore:adder|:59
- 7 - A 19 OR2 0 3 0 1 |CNT10:U~148|LPM_ADD_SUB:79|addcore:adder|:68
- 4 - A 19 DFFE 1 3 1 1 |CNT10:U~148|cqi3 (|CNT10:U~148|:9)
- 5 - A 19 DFFE 1 3 1 3 |CNT10:U~148|cqi2 (|CNT10:U~148|:10)
- 6 - A 19 DFFE 1 3 1 3 |CNT10:U~148|cqi1 (|CNT10:U~148|:11)
- 1 - A 19 DFFE 1 1 1 4 |CNT10:U~148|cqi0 (|CNT10:U~148|:12)
- 2 - A 19 DFFE 1 3 0 5 |CNT10:U~148|C_sig (|CNT10:U~148|:13)
- 3 - A 19 OR2 ! 0 4 0 4 |CNT10:U~148|:52
- 6 - A 21 AND2 0 3 0 1 |CNT10:U~165|LPM_ADD_SUB:79|addcore:adder|:59
- 4 - A 21 OR2 0 3 0 1 |CNT10:U~165|LPM_ADD_SUB:79|addcore:adder|:68
- 1 - A 21 DFFE 1 3 1 1 |CNT10:U~165|cqi3 (|CNT10:U~165|:9)
- 8 - A 21 DFFE 1 3 1 3 |CNT10:U~165|cqi2 (|CNT10:U~165|:10)
- 3 - A 21 DFFE 1 3 1 3 |CNT10:U~165|cqi1 (|CNT10:U~165|:11)
- 7 - A 21 DFFE 1 1 1 4 |CNT10:U~165|cqi0 (|CNT10:U~165|:12)
- 5 - A 21 DFFE 1 3 1 0 |CNT10:U~165|C_sig (|CNT10:U~165|:13)
- 2 - A 21 OR2 ! 0 4 0 4 |CNT10:U~165|:52
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\eda38\k4\plj\count10_8.rpt
count10_8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 6/ 96( 6%) 10/ 48( 20%) 0/ 48( 0%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 1/ 96( 1%) 3/ 48( 6%) 5/ 48( 10%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\eda38\k4\plj\count10_8.rpt
count10_8
** CLOCK SIGNALS **
Type Fan-out Name
DFF 6 |CNT10:U|C_sig
DFF 6 |CNT10:U~56|C_sig
DFF 6 |CNT10:U~80|C_sig
DFF 6 |CNT10:U~97|C_sig
DFF 6 |CNT10:U~114|C_sig
DFF 6 |CNT10:U~131|C_sig
DFF 6 |CNT10:U~148|C_sig
INPUT 5 CLK
Device-Specific Information: f:\eda38\k4\plj\count10_8.rpt
count10_8
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 33 CLR
Device-Specific Information: f:\eda38\k4\plj\count10_8.rpt
count10_8
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
ENA : INPUT;
-- Node name is 'CARRY_OUT'
-- Equation name is 'CARRY_OUT', type is output
CARRY_OUT = _LC5_A21;
-- Node name is 'CLR~1'
-- Equation name is 'CLR~1', location is LC1_B13, type is buried.
-- synthesized logic cell
!_LC1_B13 = _LC1_B13~NOT;
_LC1_B13~NOT = LCELL(!CLR);
-- Node name is 'Q0'
-- Equation name is 'Q0', type is output
Q0 = _LC6_B10;
-- Node name is 'Q1'
-- Equation name is 'Q1', type is output
Q1 = _LC2_B10;
-- Node name is 'Q2'
-- Equation name is 'Q2', type is output
Q2 = _LC1_B10;
-- Node name is 'Q3'
-- Equation name is 'Q3', type is output
Q3 = _LC4_B10;
-- Node name is 'Q4'
-- Equation name is 'Q4', type is output
Q4 = _LC1_B1;
-- Node name is 'Q5'
-- Equation name is 'Q5', type is output
Q5 = _LC3_B1;
-- Node name is 'Q6'
-- Equation name is 'Q6', type is output
Q6 = _LC8_B1;
-- Node name is 'Q7'
-- Equation name is 'Q7', type is output
Q7 = _LC7_B1;
-- Node name is 'Q8'
-- Equation name is 'Q8', type is output
Q8 = _LC1_B3;
-- Node name is 'Q9'
-- Equation name is 'Q9', type is output
Q9 = _LC7_B3;
-- Node name is 'Q10'
-- Equation name is 'Q10', type is output
Q10 = _LC6_B3;
-- Node name is 'Q11'
-- Equation name is 'Q11', type is output
Q11 = _LC5_B3;
-- Node name is 'Q12'
-- Equation name is 'Q12', type is output
Q12 = _LC6_B5;
-- Node name is 'Q13'
-- Equation name is 'Q13', type is output
Q13 = _LC4_B5;
-- Node name is 'Q14'
-- Equation name is 'Q14', type is output
Q14 = _LC5_B5;
-- Node name is 'Q15'
-- Equation name is 'Q15', type is output
Q15 = _LC1_B5;
-- Node name is 'Q16'
-- Equation name is 'Q16', type is output
Q16 = _LC5_C17;
-- Node name is 'Q17'
-- Equation name is 'Q17', type is output
Q17 = _LC7_C17;
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