s3e_analogio.vhd
来自「it is a analog i/o interface written in 」· VHDL 代码 · 共 296 行
VHD
296 行
---------------------------------------------------------------
-- Spartan-3E Kit: Analog IO Component
-- DAC component: LTC2624 4 channel, 12 bit DAC
-- ADC component: LTC1407 2 channel, 14 bit ADC
-- (c) Dr. Heinz Rongen, Forschungszentrum J黮ich, ZEL, Germany
-- H.Rongen@fz-juelich.de www.hrongen.de
---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- component S3E_AnalogIO port (
-- Clk : IN std_logic;
-- SPI_MOSI : OUT std_logic;
-- SPI_MISO : in std_logic;
-- SPI_SCK : OUT std_logic;
-- DAC_CS : OUT std_logic;
-- DAC_Clr : OUT std_logic;
-- AMP_CS : out std_logic;
-- AD_CONV : out std_logic;
-- TickAnalogIO : out std_logic;
-- Dac_A : IN std_logic_vector (11 downto 0) := x"000";
-- Dac_B : IN std_logic_vector (11 downto 0) := x"000";
-- Dac_C : IN std_logic_vector (11 downto 0) := x"000";
-- Dac_D : IN std_logic_vector (11 downto 0) := x"000";
-- Adc_A : out std_logic_vector (13 downto 0);
-- Adc_B : out std_logic_vector (13 downto 0) );
--end component;
--Please also connect:
-- SPI_SS_B <= '1';
-- SF_CE0 <= '1';
-- FPGA_INIT_B <= '1';
-------------------------------------------------------------
entity S3E_AnalogIO is
port (
Clk : IN std_logic;
SPI_MOSI : OUT std_logic;
SPI_MISO : in std_logic;
SPI_SCK : OUT std_logic;
DAC_CS : OUT std_logic;
DAC_Clr : OUT std_logic;
AMP_CS : out std_logic;
AD_CONV : out std_logic;
TickAnalogIO: out std_logic;
Dac_A : IN std_logic_vector (11 downto 0) := x"000";
Dac_B : IN std_logic_vector (11 downto 0) := x"000";
Dac_C : IN std_logic_vector (11 downto 0) := x"000";
Dac_D : IN std_logic_vector (11 downto 0) := x"000";
Adc_A : out std_logic_vector (13 downto 0);
Adc_B : out std_logic_vector (13 downto 0)
);
end S3E_AnalogIO;
--------------------------------------
architecture Behav of S3E_AnalogIO is
type EVENT_TYPE is (S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15,
S16, S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31 );
signal sDacState : EVENT_TYPE;
signal Clk2 : std_logic;
signal sData : std_logic_vector (31 downto 0);
begin
pClk2: process (Clk)
begin
if rising_edge(Clk) then
Clk2 <= not Clk2;
end if;
end process;
DAC_Clr <= '1';
pDAC: process (Clk2, sDacState)
constant kDacA : std_logic_vector(7 downto 0) := "00110000"; -- update immediately
constant kDacB : std_logic_vector(7 downto 0) := "00110001";
constant kDacC : std_logic_vector(7 downto 0) := "00110010";
constant kDacD : std_logic_vector(7 downto 0) := "00110011";
constant kAmpD : std_logic_vector(7 downto 0) := "00010001";
variable bitnr : integer;
variable i : integer;
begin
if rising_edge (Clk2)
then
case sDacState is
when S0 => Dac_CS <= '1';
AMP_CS <= '1';
AD_CONV <= '0';
SPI_SCK <= '0';
SPI_MOSI <= '0';
sDacState <= S1;
-- DAC_A
when S1 => Dac_CS <= '0'; -- Prepare
bitnr := 0;
sData <= "00000000" & kDacA & Dac_A & "0000";
sDacState <= S2;
when S2 => Dac_CS <= '0'; -- LOOP: set Data
SPI_SCK <= '0';
SPI_MOSI <= sData(31);
sData <= sData (30 downto 0) & '0';
sDacState <= S3;
when S3 => SPI_SCK <= '1';
bitnr := bitnr +1;
if (bitnr < 32) then -- Set Clock
sDacState <= S2;
else
sDacState <= S4;
end if;
when S4 => Dac_CS <= '1'; -- OK
SPI_SCK <= '0';
sDacState <= S5;
-- DAC_B ------------------------------------------------
when S5 => Dac_CS <= '0'; -- Prepare
bitnr := 0;
sData <= "00000000" & kDacB & Dac_B & "0000";
sDacState <= S6;
when S6 => Dac_CS <= '0'; -- LOOP: set Data
SPI_SCK <= '0';
SPI_MOSI <= sData(31);
sData <= sData (30 downto 0) & '0';
sDacState <= S7;
when S7 => SPI_SCK <= '1';
bitnr := bitnr +1;
if (bitnr < 32) then -- Set Clock
sDacState <= S6;
else
sDacState <= S8;
end if;
when S8 => Dac_CS <= '1'; -- OK
SPI_SCK <= '0';
sDacState <= S9;
-- DAC_C -------------------------------------------------
when S9 => Dac_CS <= '0'; -- Prepare
bitnr := 0;
sData <= "00000000" & kDacC & Dac_C & "0000";
sDacState <= S10;
when S10 => Dac_CS <= '0'; -- LOOP: set Data
SPI_SCK <= '0';
SPI_MOSI <= sData(31);
sData <= sData (30 downto 0) & '0';
sDacState <= S11;
when S11 => SPI_SCK <= '1';
bitnr := bitnr +1;
if (bitnr < 32) then -- Set Clock
sDacState <= S10;
else
sDacState <= S12;
end if;
when S12 => Dac_CS <= '1'; -- OK
SPI_SCK <= '0';
sDacState <= S13;
-- DAC_D -------------------------------------------------------
when S13 => Dac_CS <= '0'; -- Prepare
bitnr := 0;
sData <= "00000000" & kDacD & Dac_D & "0000";
sDacState <= S14;
when S14 => Dac_CS <= '0'; -- LOOP: set Data
SPI_SCK <= '0';
SPI_MOSI <= sData(31);
sData <= sData (30 downto 0) & '0';
sDacState <= S15;
when S15 => SPI_SCK <= '1';
bitnr := bitnr +1;
if (bitnr < 32) then -- Set Clock
sDacState <= S14;
else
sDacState <= S16;
end if;
when S16 => Dac_CS <= '1'; -- OK
SPI_SCK <= '0';
sDacState <= S17;
--- Prog. Gain Amplifier ---------------------------------------
when S17 => AMP_CS <= '0'; -- Prepare
bitnr := 0;
sData <= kAmpD & "00000000" & "00000000" & "00000000";
i := 0;
sDacState <= S18;
when S18 => Dac_CS <= '0'; -- LOOP: set Data
SPI_SCK <= '0';
SPI_MOSI <= sData(31);
i := i + 1;
if (i>1) then
bitnr := bitnr +1;
sData <= sData (30 downto 0) & '0';
i := 0;
sDacState <= S19;
end if;
when S19 => SPI_SCK <= '1';
i := i + 1;
if (i>1) then
if (bitnr < 8) then -- Set Clock
i := 0;
sDacState <= S18;
else
i := 0;
sDacState <= S20;
end if;
end if;
when S20 => AMP_CS <= '1'; -- OK
SPI_SCK <= '0';
i := i + 1;
if (i>1) then
i := 0;
sDacState <= S21;
end if;
--- ADC ----------------------------------------------------------
when S21 => AD_CONV <= '1'; -- Prepare: ADC Convert
SPI_SCK <= '0';
sDacState <= S22;
when S22 => AD_CONV <= '1'; -- 1. Clk
SPI_SCK <= '1';
sDacState <= S23;
when S23 => AD_CONV <= '0'; --
SPI_SCK <= '0';
bitnr := 0;
sDacState <= S24;
when S24 => AD_CONV <= '0';
SPI_SCK <= '1';
sDacState <= S25;
when S25 => AD_CONV <= '0';
SPI_SCK <= '0';
sData <= sData (30 downto 0) & SPI_MISO;
bitnr := bitnr + 1;
if (bitnr < 33) then
sDacState <= S24;
else
sDacState <= S26;
end if;
when S26 => AD_CONV <= '0';
SPI_SCK <= '0';
Adc_A <= sData(31) & not sData (30 downto 18);
Adc_B <= sdata(15) & not sData (14 downto 2);
sDacState <= S27;
---------------------------------------------------------
when S27 => TickAnalogIO <= '1';
sDacState <= S28;
when S28 => TickAnalogIO <= '0';
sDacState <= S0;
when others => sDacState <= S0;
end case;
end if;
end process;
end Behav;
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