command.log

一个用TCL/TK写的用于verilog的集成编辑环境.

#@ set sdfout_time_scale   1.0
#@ set sdfout_min_rise_net_delay   0.
#@ set sdfout_min_fall_net_delay   0.
#@ set sdfout_min_rise_cell_delay   0.
#@ set sdfout_min_fall_cell_delay   0.
#@ set sdfout_write_to_output   "false"
#@ set sdfout_allow_non_positive_constraints   "false"
#@ set sdfin_top_instance_name   ""
#@ set sdfin_min_rise_net_delay   0.
#@ set sdfin_min_fall_net_delay   0. 
#@ set sdfin_min_rise_cell_delay   0.
#@ set sdfin_min_fall_cell_delay   0.
#@ set sdfin_rise_net_delay_type   "maximum"
#@ set sdfin_fall_net_delay_type   "maximum"
#@ set sdfin_rise_cell_delay_type   "maximum"
#@ set sdfin_fall_cell_delay_type   "maximum"
#@ set site_info_file ${synopsys_root}/admin/license/site_info
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@   alias site_info sh cat $site_info_file
#@ } else {
#@   alias site_info "sh cat site_info_file"
#@ }
#@ set hdl_naming_threshold   20
#@ set template_naming_style   "%s_%p"
#@ set template_parameter_style   "%s%d"
#@ set template_separator_style   "_"
#@ set design_library_file   ".synopsys_vss.setup"
#@ set verilogout_equation "false" 
#@ set verilogout_ignore_case   "false"
#@ set verilogout_no_tri   "false"
#@ set verilogout_single_bit   "false"
#@ set verilogout_higher_designs_first   "FALSE"
#@ set verilogout_levelize   "FALSE"
#@ set verilogout_include_files   {}
#@ set verilogout_unconnected_prefix   "SYNOPSYS_UNCONNECTED_"
#@ set verilogout_show_unconnected_pins   "FALSE"
#@ set verilogout_no_negative_index   "FALSE"
#@ set vhdlout_architecture_name   "SYN_%a_%u"
#@ set vhdlout_bit_type   "std_logic"
#@ set vhdlout_bit_type_resolved   "TRUE"
#@ set vhdlout_bit_vector_type   "std_logic_vector"
#@ set vhdlout_conversion_functions   {}
#@ set vhdlout_dont_write_types   "FALSE"
#@ set vhdlout_equations   "FALSE"
#@ set vhdlout_one_name   "'1'"
#@ set vhdlout_package_naming_style   "CONV_PACK_%d"
#@ set vhdlout_preserve_hierarchical_types   "VECTOR"
#@ set vhdlout_separate_scan_in   "FALSE"
#@ set vhdlout_single_bit   "USER"
#@ set vhdlout_target_simulator   ""
#@ set vhdlout_three_state_name   "'Z'"
#@ set vhdlout_three_state_res_func   ""
#@ set vhdlout_time_scale   1.0
#@ set vhdlout_top_configuration_arch_name   "A"
#@ set vhdlout_top_configuration_entity_name   "E"
#@ set vhdlout_top_configuration_name  "CFG_TB_E"
#@ set vhdlout_unknown_name   "'X'"
#@ set vhdlout_upcase   "FALSE"
#@ set vhdlout_use_packages   {IEEE.std_logic_1164}
#@ set vhdlout_wired_and_res_func   ""
#@ set vhdlout_wired_or_res_func   ""
#@ set vhdlout_write_architecture   "TRUE"
#@ set vhdlout_write_components   "TRUE"
#@ set vhdlout_write_entity   "TRUE"
#@ set vhdlout_write_top_configuration   "FALSE"
#@ set vhdlout_synthesis_off   "TRUE"
#@ set vhdlout_zero_name   "'0'"
#@ set vhdlout_levelize   "FALSE"
#@ set vhdlout_dont_create_dummy_nets   "FALSE"
#@ set vhdlout_follow_vector_direction   "FALSE"
#@ 
#@ # variables pertaining to VHDL library generation 
#@ set vhdllib_timing_mesg   "true"
#@ set vhdllib_timing_xgen   "false"
#@ set vhdllib_timing_checks   "true"
#@ set vhdllib_negative_constraint   "false"
#@ set vhdllib_glitch_handle   "true"
#@ set vhdllib_pulse_handle   "use_vhdllib_glitch_handle"
#@ # /*vhdllib_architecture = {FTBM, UDSM, FTSM, FTGS, VITAL}; */
#@ set vhdllib_architecture   {UDSM, FTSM, FTGS, VITAL}
#@ set vhdllib_tb_compare   0
#@ set vhdllib_tb_x_eq_dontcare   FALSE
#@ set vhdllib_logic_system   "ieee-1164"
#@ set vhdllib_logical_name   ""
#@ 
#@ # variables pertaining to technology library processing 
#@ set read_db_lib_warnings   FALSE
#@ set read_translate_msff    TRUE
#@ set libgen_max_differences   -1
#@ 
#@ #
#@ #        View Variable Group:
#@ #
#@ #        These variables define the behavior of the Design_Analyzer.
#@ #        Each user may wish to customize the cursor color, or , , etc. of the
#@ #        viewer in his/her own .synopsys file.
#@ #
#@ #
#@ set view_maximum_route_grids   0 
#@ set view_dialogs_modal   "true" 
#@ set view_disable_error_windows   "false" 
#@ set view_error_window_count   6 
#@ set view_log_file   "" 
#@ set view_busy_during_selection   "true" 
#@ set view_set_cursor_area   5 
#@ set view_cache_images   "true" 
#@ set view_draw_text_breakpoint   0.01 
#@ set view_use_integer_scaling   "false" 
#@ set view_use_x_routines   "true" 
#@ set view_disable_output   "false" 
#@ #set view_arch_types   {sparcOS5, hpux10, apollo, decmips, hp700, mips, necmips, rs6000, sgimips, sonymips, sun3, sparc} 
#@ set view_icon_path ${init_path}/icons
#@ set view_background   "black" 
#@ set view_disable_cursor_warping   "true" 
#@ set view_watcher ${bin_path}/da_watcher_exec
#@ set da_ref_manual "synth/daptr/toc.pdf"
#@ set view_command_win_max_lines   1000 
#@ set view_select_separator   "  -  " 
#@ set view_select_default_message   "Left Button: Select   -   Middle Button: Add/Modify Select   -   Right Button: Menu"
#@ set view_on_line_doc_cmd ${synopsys_root}/sold
#@ set view_info_search_cmd ${synopsys_root}/infosearch/scripts/InfoSearch
#@ set view_script_submenu_items   {}
#@ set x11_set_cursor_number   -1 
#@ set x11_set_cursor_foreground   "" 
#@ set x11_set_cursor_background   "" 
#@ set view_set_selecting_color    "" 
#@ set view_use_small_cursor   "" 
#@ # added for star 12763
#@ set view_tools_menu_items   {}           
#@ # affect the HDL Text Viewer
#@ set text_unselect_on_button_press   "true"
#@ set text_editor_command   "xterm -fn 8x13 -e vi %s &" 
#@ set test_design_analyzer_uses_insert_scan   "true"
#@ 
#@ #
#@ # If you like emacs, uncomment the next line 
#@ # set text_editor_command  "emacs -fn 8x13 %s &" ; 
#@ 
#@ # You can delete pairs from this list, but you can't add new ones
#@ # unless you also update the UIL files.  So, customers can not add
#@ # dialogs to this list, only Synopsys can do that.
#@ #
#@ set view_independent_dialogs   { "test_report",    " Test Reports ",                              "report_print",   " Report ",                              "report_options", " Report Options ",                              "report_win",     " Report Output ",                              "manual_page",    " Manual Page " } 
#@ 
#@ # if color Silicon Graphics workstation 
#@ if { [info exists x11_vendor_string] && [info exists x11_is_color]} {
#@   if {  $x11_vendor_string == "Silicon" && $x11_is_color == "true" } {
#@     set x11_set_cursor_foreground "magenta" 
#@     set view_use_small_cursor "true"
#@     set view_set_selecting_color "white"
#@   } 
#@ } 
#@ 
#@ # if running on an Apollo machine 
#@ set found_x11_vendor_string_apollo 0
#@ set found_arch_apollo 0
#@ if { [info exists x11_vendor_string]} {
#@   if { $x11_vendor_string == "Apollo "} {
#@     set found_x11_vendor_string_apollo 1
#@   }
#@ }
#@ if { [info exists arch]} {
#@   if { $arch == "apollo"} {
#@     set found_arch_apollo 1
#@   }
#@ }
#@ if { $found_x11_vendor_string_apollo == 1 || $found_arch_apollo == 1} {
#@   set enable_page_mode  "false"
#@ } else {
#@   set enable_page_mode  "true"
#@ }
#@ 
#@ # don't work around this bug on the Apollo 
#@ if { $found_x11_vendor_string_apollo == 1} {
#@   set view_extend_thick_lines "false"
#@ } else {
#@   set view_extend_thick_lines "true" 
#@ }
#@ 
#@ #
#@ #        Suffix Variable Group:
#@ #
#@ #        Suffixes recognized by the Design Analyzer menu in file choices
#@ #
#@ if { $synopsys_program_name == "design_vision" || $synopsys_program_name == "psyn_gui" } {
#@   # For star 93040 do NOT include NET in list, 108991 : pdb suffix added
#@   set view_read_file_suffix    {db gdb sdb pdb edif eqn fnc lsi mif pla st tdl v vhd vhdl xnf}
#@ } else {
#@   set view_read_file_suffix    {db gdb sdb edif eqn fnc lsi mif NET pla st tdl v vhd vhdl xnf} 
#@ }
#@ 
#@ set view_analyze_file_suffix    {v vhd vhdl} 
#@ set view_write_file_suffix   {gdb db sdb do edif eqn fnc lsi NET neted pla st tdl v vhd vhdl xnf} 
#@ set view_execute_script_suffix   {.script .scr .dcs .dcv .dc .con} 
#@ set view_arch_types   {sparcOS5 hpux10 rs6000 sgimips} 
#@ 
#@ #
#@ #        links_to_layout Variable Group:
#@ #
#@ #        These variables affect the read_timing, write_timing
#@ #        set_annotated_delay, compile, create_wire_load and reoptimize_design
#@ #        commands.
#@ #
#@ set rtl_load_resistance_factor 0.0
#@ set auto_wire_load_selection   "true" 
#@ set compile_create_wire_load_table   "false" 
#@ 
#@ #      power Variable Group:
#@ #
#@ #        These variables affect the behavior of power analysis.
#@ #
#@ #
#@ 
#@ set power_keep_license_after_power_commands   "false"
#@ set power_rtl_saif_file                       "power_rtl.saif"
#@ set power_sdpd_saif_file                      "power_sdpd.saif"
#@ set power_preserve_rtl_hier_names             "false"
#@ set power_do_not_size_icg_cells               "false"
#@ set power_hdlc_do_not_split_cg_cells          "false"
#@ 
#@ #      BC Variable Group:
#@ #
#@ #        These variables affect the BC behavior
#@ #
#@ #
#@ 
#@ #
#@ # BCView
#@ # 
#@ set bc_enable_analysis_info           "false"
#@ 
#@ #
#@ # Scheduling
#@ # 
#@ set bc_enable_chaining                "true"
#@ set bc_enable_multi_cycle             "true"
#@ set bc_enable_speculative_execution   "false"
#@ 
#@ 
#@ #
#@ # Control Generation
#@ #
#@ set bc_fsm_coding_style               "one_hot"
#@ 
#@ #
#@ # Netlisting
#@ #
#@ #Ki-Seok: removed the following 3 variables: Jan. 1999
#@ #/*
#@ #set bc_no_reset_on_datapath           "true"
#@ #set bc_clears_all_registers           "false"
#@ #set bc_connect_reset                  "true"
#@ #*/
#@ 
#@ #/*
#@ # * Timing (bc_time_design and timing estimates during scheduling)
#@ # */
#@ #/* Removed by Suhrid A. Wadekar  Feb. 11, 1999.
#@ # * bc_preserved_functions_map_effort is no longer supported
#@ # */
#@ #/*
#@ #set bc_preserved_functions_map_effort         "medium"
#@ #*/
#@ set bc_time_all_sequential_op_bindings        "false"
#@ set bc_estimate_mux_input                     4
#@ set bc_estimate_timing_effort                 "high"
#@ 
#@ #/*
#@ # * Memories
#@ # */
#@ set bc_allow_shared_memories          "false"
#@ set bc_constrain_signal_memories      "false"
#@ set bc_detect_memory_accesses         "false"
#@ set bc_detect_array_accesses          "false"
#@ set bc_chain_read_into_mem            "true"
#@ set bc_chain_read_into_oper           "true"
#@ 
#@ #/*
#@ # * Logic grouping
#@ # */
#@ set bc_group_eql_logic                "true"
#@ set bc_group_index_logic              "true"
#@ set bc_use_registerfiles              "false"
#@ 
#@ #
#@ #  Reporting
#@ # 
#@ set bc_report_filter                  ""
#@ 
#@ #
#@ # RTLout debug mode
#@ #
#@ set vhdlout_debug_mode "false"
#@ set verilogout_debug_mode "false"
#@ 
#@ #
#@ # RTLout i/o trace
#@ #
#@ set bc_add_io_trace "false"
#@ 
#@ # Synthesizable RTLOUT variables
#@ set bc_synrtl_map_to_gtech "true"
#@ set bc_synrtl_write_precompiled_designware "true"
#@ set bc_synrtl_write_preserved_functions "true"
#@ set bc_synrtl_write_dcsh_and_dctcl "false"
#@ 
#@ # SystemC related variables
#@ set systemcout_levelize "true"
#@ set systemcout_debug_mode "false"
#@ 
#@ # ACS Variables
#@ if { [info exists acs_work_dir] } {
#@   set acs_work_dir                            [pwd]
#@   set acs_hdl_source                          {}
#@   set acs_verilog_extensions                  {.v}
#@   set acs_vhdl_extensions                     {.vhd}
#@   set acs_exclude_extensions                  {}
#@   set acs_exclude_list                        {}
#@   set acs_area_report_suffix                  "area"
#@   set acs_budgeted_cstr_suffix                "con"
#@   set acs_compile_script_suffix               "autoscr"
#@   set acs_constraint_file_suffix              "con"
#@   set acs_cstr_report_suffix                  "cstr"
#@   set acs_db_suffix                           "db"
#@   set acs_log_file_suffix                     "log"
#@   set acs_makefile_name                       "Makefile"
#@   set acs_override_script_suffix              "scr"
#@   set acs_qor_report_suffix                   "qor"
#@   set acs_timing_report_suffix                "tim"
#@   set acs_user_compile_strategy_script_suffix "compile"
#@   set acs_global_user_compile_strategy_script "default"
#@   set acs_budget_script_file_suffix           "btcl"
#@   set acs_budget_output_file_suffix           "btcl.out"
#@   set acs_use_lsf                             "false"
#@   set acs_script_mode                         "dctcl"
#@   set acs_default_pass_name                   "pass"