command.log

一个用TCL/TK写的用于verilog的集成编辑环境.

#@ set jtag_port_drive_limit  6
#@ set jtag_manufacturer_id  0
#@ set jtag_version_number  0
#@ set jtag_part_number  65535
#@ set jtag_test_data_in_port_naming_style  "jtag_tdi%s"
#@ set jtag_test_data_out_port_naming_style  "jtag_tdo%s"
#@ set jtag_test_mode_select_port_naming_style  "jtag_tms%s"
#@ set jtag_test_clock_port_naming_style  "jtag_tck%s"
#@ set jtag_test_reset_port_naming_style   "jtag_trst%s"
#@ 
#@ 
#@ 
#@ #
#@ #       Create_Test_Patterns Variable Group:
#@ #
#@ #       These variables affect the create_test_patterns command.
#@ #
#@ # From Peace on, the "atpg_test_asynchronous_pins" is obsolete
#@ # set atpg_test_asynchronous_pins  "true"
#@ 
#@ set atpg_bidirect_output_only  "false"
#@ 
#@ 
#@ #
#@ #       Write_Test Variable Group:
#@ #
#@ #       These variables affect output of the WRITE_TEST command.
#@ #
#@ set write_test_input_dont_care_value  "X"
#@ set write_test_vector_file_naming_style  "%s_%d.%s"
#@ set write_test_scan_check_file_naming_style   "%s_schk.%s"
#@ set write_test_pattern_set_naming_style  "TC_Syn_%d"
#@ set write_test_max_cycles  0
#@ set write_test_max_scan_patterns  0
#@ # /*retain "tssi_ascii" (equivalent to "tds") for backward compatability */
#@ set write_test_formats   {synopsys tssi_ascii tds verilog vhdl wgl}
#@ set write_test_include_scan_cell_info  "true"
#@ set write_test_round_timing_values "true"
#@ 
#@ #
#@ #       Schematic and EDIF and Hdl Variable Groups:
#@ #
#@ #       These variables affect the schematics created by the
#@ #       create_schematic command, define the behavior of the
#@ #       DC system EDIF interface, and are for controlling hdl
#@ #       reading.
#@ #
#@ set bus_dimension_separator_style  {][}
#@ set bus_naming_style  {%s[%d]}
#@ 
#@ 
#@ #
#@ #       Schematic and EDIF Variable Groups:
#@ #
#@ #       These variables affect the schematics created by the
#@ #       create_schematic command and define the behavior of
#@ #       the DC system EDIF interface.
#@ #
#@ set bus_range_separator_style  ":"
#@ 
#@ 
#@ #
#@ # EDIF and Io Variable Groups:
#@ #
#@ # These variables define the behavior of the DC system EDIF interface and
#@ # define the behavior of the DC system interfaces, i.e. LSI, Mentor, TDL, SGE,# etc.
#@ 
#@ set bus_inference_descending_sort  "true"
#@ set bus_inference_style  ""
#@ set write_name_nets_same_as_ports  "false"
#@ #
#@ #       Schematic Variable Group:
#@ #
#@ #       These variables affect the schematics created by the
#@ #       create_schematic command.
#@ #
#@ set font_library  "1_25.font"
#@ set generic_symbol_library  "generic.sdb"
#@ set gen_max_ports_on_symbol_side  0
#@ set duplicate_ports   "false"
#@ set sheet_sizes  {A B C D E infinite mentor_maximum sge_maximum}
#@ set single_group_per_sheet  "false"
#@ set use_port_name_for_oscs  "true"
#@ set gen_bussing_exact_implicit  "false"
#@ set gen_cell_pin_name_separator  "/"
#@ set gen_max_compound_name_length  256
#@ set gen_show_created_symbols  "false"
#@ set gen_match_ripper_wire_widths  "false"
#@ set gen_show_created_busses  "false"
#@ set gen_dont_show_single_bit_busses  "false"
#@ set gen_single_osc_per_name  "false"
#@ set gen_create_netlist_busses  "true"
#@ # This setting will be overwritten to true below when using
#@ # Design Vision or Psyn Gui
#@ set sort_outputs  "false"
#@ if { ( [string compare $synopsys_program_name "design_vision"] == 0 ) || 
#@      ( [string compare $synopsys_program_name "psyn_gui"] == 0 ) } {
#@   set dv_enable_conservative_invalidate "true"
#@ }
#@ set gen_open_name_prefix  "Open"
#@ set gen_open_name_postfix  ""
#@ set default_schematic_options  "-size infinite"
#@ # This setting makes gen use the old way to annotate schematics for
#@ #   everything except sheets, which is fast enough.
#@ #
#@ set annotation_control  64
#@ 
#@ #
#@ #       Plot Variable Group:
#@ #
#@ #       These variables define the operating system and plotter
#@ #       interface to the Design Compiler.  These should be set at
#@ #       installation time, if needed, and then changed only if you
#@ #       start using a new type of plotter.
#@ #
#@ #       These four variables must be changed if you use a larger or
#@ #       smaller plotter or printer:
#@ #
#@ #       plotter_maxx, plotter_maxy, plotter_minx, plotter_miny
#@ #
#@ #       See the group of site-specific variables at the top of this
#@ #       file to set the name of your printer or plotter.
#@ #
#@ #
#@ 
#@ set plot_orientation  "best_fit"
#@ set plotter_maxx   584
#@ set plotter_maxy   764
#@ set plotter_minx   28
#@ set plotter_miny   28
#@ set plot_scale_factor   100
#@ set plot_box   "false"
#@ 
#@ 
#@ #
#@ #       Io Variable Group:
#@ #
#@ #       These variables define the behavior of the DC system
#@ #       interfaces, i.e. LSI, Mentor, TDL, SGE, etc.
#@ #
#@ set db2sge_output_directory  ""
#@ set db2sge_scale  "2"
#@ set db2sge_overwrite   "true"
#@ set db2sge_display_symbol_names  "false"
#@ 
#@ 
#@ set db2sge_display_pin_names  "false"
#@ set db2sge_display_instance_names   "false"
#@ set db2sge_use_bustaps   "false"
#@ set db2sge_use_compound_names   "true"
#@ set db2sge_bit_type   "std_logic"
#@ set db2sge_bit_vector_type   "std_logic_vector"
#@ set db2sge_one_name   "'1'"
#@ set db2sge_zero_name  "'0'"
#@ set db2sge_unknown_name  "'X'"
#@ set db2sge_target_xp  "false"
#@ set db2sge_tcf_package_file  "synopsys_tcf.vhd"
#@ set db2sge_use_lib_section  ""
#@ set db2sge_script  ""
#@ set db2sge_command  ""
#@ set equationout_and_sign  "*"
#@ set equationout_or_sign  "+"
#@ set equationout_postfix_negation  "true"
#@ set lsiin_net_name_prefix  "NET_"
#@ set lsiout_inverter_cell  ""
#@ set lsiout_upcase  "true"
#@ set mentor_bidirect_value  "INOUT"
#@ set mentor_do_path  ""
#@ set mentor_input_output_property_name  "PINTYPE"
#@ set mentor_input_value  "IN"
#@ set mentor_logic_one_value  "1SF"
#@ set mentor_logic_zero_one_property_name  "INIT"
#@ set mentor_logic_zero_value  "0SF"
#@ set mentor_output_value  "OUT"
#@ set mentor_primitive_property_name  "PRIMITIVE"
#@ set mentor_primitive_property_value  "MODULE"
#@ set mentor_reference_property_name  "COMP"
#@ set mentor_search_path   ""
#@ set mentor_write_symbols   "true"
#@ set pla_read_create_flip_flop   "false"
#@ set tdlout_upcase   "true"
#@ set xnfout_constraints_per_endpoint   "50"
#@ set xnfout_default_time_constraints   true
#@ set xnfout_clock_attribute_style   "CLK_ONLY"
#@ set xnfout_library_version  ""
#@ set xnfin_family   "4000"
#@ set xnfin_ignore_pins   "GTS GSR GR"
#@ set xnfin_dff_reset_pin_name             "RD"
#@ set xnfin_dff_set_pin_name               "SD"
#@ set xnfin_dff_clock_enable_pin_name      "CE"
#@ set xnfin_dff_data_pin_name              "D"
#@ set xnfin_dff_clock_pin_name             "C"
#@ set xnfin_dff_q_pin_name                 "Q"
#@ 
#@ 
#@ #
#@ #       EDIF Variable Group:
#@ #
#@ #       These variables define the behavior of the DC system
#@ #       EDIF interface.
#@ #
#@ set bus_extraction_style   {%s[%d:%d]}
#@ set edifin_autoconnect_offpageconnectors   "false"
#@ set edifin_autoconnect_ports   "false"
#@ set edifin_dc_script_flag   ""
#@ set edifin_delete_empty_cells   "true"
#@ set edifin_delete_ripper_cells   "true"
#@ set edifin_ground_net_name   ""
#@ set edifin_ground_net_property_name   ""
#@ set edifin_ground_net_property_value   ""
#@ set edifin_ground_port_name   ""
#@ set edifin_instance_property_name    ""
#@ set edifin_portinstance_disabled_property_name   ""
#@ set edifin_portinstance_disabled_property_value   ""
#@ set edifin_portinstance_property_name   ""
#@ set edifin_power_net_name  ""
#@ set edifin_power_net_property_name  ""
#@ set edifin_power_net_property_value  ""
#@ set edifin_power_port_name  ""
#@ set edifin_use_identifier_in_rename  "false"
#@ set edifin_view_identifier_property_name  ""
#@ set edifin_lib_logic_1_symbol  ""
#@ set edifin_lib_logic_0_symbol  ""
#@ set edifin_lib_in_port_symbol  ""
#@ set edifin_lib_out_port_symbol  ""
#@ set edifin_lib_inout_port_symbol  ""
#@ set edifin_lib_in_osc_symbol  ""
#@ set edifin_lib_out_osc_symbol  ""
#@ set edifin_lib_inout_osc_symbol  ""
#@ set edifin_lib_mentor_netcon_symbol  ""
#@ set edifin_lib_ripper_bits_property  ""
#@ set edifin_lib_ripper_bus_end  ""
#@ set edifin_lib_ripper_cell_name  ""
#@ set edifin_lib_ripper_view_name  ""
#@ set edifin_lib_route_grid  1024
#@ set edifin_lib_templates  {}
#@ set edifout_dc_script_flag  ""
#@ set edifout_design_name  "Synopsys_edif"
#@ set edifout_designs_library_name  "DESIGNS"
#@ set edifout_display_instance_names  "false"
#@ set edifout_display_net_names  "false"
#@ set edifout_external  "true"
#@ set edifout_external_graphic_view_name  "Graphic_representation"
#@ set edifout_external_netlist_view_name  "Netlist_representation"
#@ set edifout_external_schematic_view_name  "Schematic_representation"
#@ set edifout_ground_name  "logic_0"
#@ set edifout_ground_net_name  ""
#@ set edifout_ground_net_property_name  ""
#@ set edifout_ground_net_property_value  ""
#@ set edifout_ground_pin_name  "logic_0_pin"
#@ set edifout_ground_port_name  "GND"
#@ set edifout_instance_property_name   ""
#@ set edifout_instantiate_ports  "false"
#@ set edifout_library_graphic_view_name  "Graphic_representation"
#@ set edifout_library_netlist_view_name  "Netlist_representation"
#@ set edifout_library_schematic_view_name  "Schematic_representation"
#@ set edifout_merge_libraries  "false"
#@ set edifout_multidimension_arrays  "false"
#@ set edifout_name_oscs_different_from_ports  "false"
#@ set edifout_name_rippers_same_as_wires  "false"
#@ set edifout_netlist_only   "false"
#@ set edifout_no_array   "false"
#@ set edifout_numerical_array_members   "false"
#@ set edifout_pin_direction_in_value   ""
#@ set edifout_pin_direction_inout_value   ""
#@ set edifout_pin_direction_out_value   ""
#@ set edifout_pin_direction_property_name   ""
#@ set edifout_pin_name_property_name   ""
#@ set edifout_portinstance_disabled_property_name    ""
#@ set edifout_portinstance_disabled_property_value    ""
#@ set edifout_portinstance_property_name    ""
#@ set edifout_power_and_ground_representation   "cell"
#@ set edifout_power_name    "logic_1"
#@ set edifout_power_net_name   ""
#@ set edifout_power_net_property_name   ""
#@ set edifout_power_net_property_value   ""
#@ set edifout_power_pin_name    "logic_1_pin"
#@ set edifout_power_port_name    "VDD"
#@ set edifout_skip_port_implementations   "false"
#@ set edifout_target_system   ""
#@ set edifout_top_level_symbol   "true"
#@ set edifout_translate_origin   ""
#@ set edifout_unused_property_value   ""
#@ set edifout_write_attributes   "false"
#@ set edifout_write_constraints   "false"
#@ set edifout_write_properties_list   {}
#@ set read_name_mapping_nowarn_libraries   {}
#@ set write_name_mapping_nowarn_libraries    {}
#@ 
#@ #
#@ #       Hdl and Vhdlio Variable Groups:
#@ #
#@ #       These variables are for controlling hdl reading, writing,
#@ #       and optimizing.
#@ #
#@ set hdlin_enable_presto FALSE
#@ set hdlin_advisor_directory   "."
#@ set bus_minus_style   "-%d"
#@ set hdlin_write_gtech_design_directory   "."
#@ set hdlin_enable_analysis_info   "false"
#@ set hdlin_hide_resource_line_numbers   FALSE
#@ set hdlin_reg_report_length   60
#@ set hdlin_auto_save_templates   FALSE
#@ set hdlin_replace_synthetic   FALSE
#@ set hdlin_dont_check_param_width FALSE
#@ set hdlin_latch_always_async_set_reset   FALSE
#@ set hdlin_ff_always_sync_set_reset   FALSE
#@ set hdlin_ff_always_async_set_reset   TRUE
#@ set hdlin_check_no_latch   FALSE
#@ set hdlin_report_inferred_modules   "true"
#@ set hdlin_reg_report_length   60
#@ set hdlin_translate_off_skip_text   false
#@ set hdlin_keep_feedback   FALSE
#@ set hdlin_keep_inv_feedback   TRUE
#@ set hdlin_infer_mux   "default"
#@ set hdlin_merge_nested_conditional_statements   false
#@ set hdlin_dont_infer_mux_for_resource_sharing   "true"
#@ set hdlin_mux_oversize_ratio   100
#@ set hdlin_mux_size_limit   32
#@ set hdlin_infer_multibit   "default_none"
#@ set hdlin_enable_vpp   false
#@ set hdlin_preserve_vpp_files   false
#@ set hdlin_vpp_temporary_directory   ""
#@ set hdlin_dont_turbo_instances_with_generics "true"
#@ set hdlin_vhdl93_concat	"true"
#@ set hdlin_enable_rtldrc_info "false"
#@ set hdl_preferred_license   ""
#@ set hdl_keep_licenses   "true"
#@ set hlo_resource_allocation   "constraint_driven"
#@ set hlo_transform_constant_multiplication   "false"
#@ set hlo_minimize_tree_delay   true 
#@ set hlo_resource_implementation   "use_fastest"
#@ set hlo_share_common_subexpressions   true 
#@ set hlo_share_effort   low 
#@ set hlo_ignore_priorities   false
#@ set sdfout_top_instance_name   ""