command.log

一个用TCL/TK写的用于verilog的集成编辑环境.

#@ ##############################################################################
#@ #
#@ 
#@ proc read_db { args } {
#@   parse_proc_arguments -args $args ra
#@ 
#@   set cmd [format {read_file -format db  [list %s]} $ra(file_names)]
#@   return [uplevel #0 $cmd]
#@ }
#@ 
#@ define_proc_attributes read_db     -info " Read one or more db files"     -permanent     -define_args {
#@       {file_names "Files to read" file_names list required}
#@       {-netlist_only "Do not read any attributes from db (ignored)" "" boolean {hidden optional}}
#@       {-library "File is a library DB (ignored)" "" boolean {hidden optional}}
#@      }
#@ 
#@ ##############################################################################
#@ #
#@ #
#@ #  PROCEDURE:   read_edif
#@ #
#@ #  ABSTRACT:    Emulate PT's read_edif command in DC: 
#@ #
#@ #  Usage:     
#@ #      read_edif            #  Read one or more edif files
#@ #        *[-complete_language]  (Use ptxr to read the file (ignored))
#@ #        file_names             (Files to read)
#@ #
#@ #
#@ ##############################################################################
#@ #
#@ proc read_edif { args } {
#@   parse_proc_arguments -args $args ra
#@ 
#@   set cmd [format {read_file -format edif  [list %s]} $ra(file_names)]
#@   return [uplevel #0 $cmd]
#@ }
#@ 
#@ define_proc_attributes read_edif     -info " Read one or more edif files"     -permanent     -define_args {
#@       {file_names "Files to read" file_names list required}
#@       {-complete_language "Use ptxr to read the file (ignored)" "" boolean {hidden optional}}
#@ }
#@ 
#@ # -- End source /tools/synopsys/2000.11/auxx/syn/.dc_procs.tcl

#@ 
#@ # Temporary fix for the LMC_HOME variable- set it to an empty string 
#@ 
#@ if { [catch {getenv LMC_HOME } __err ] != 0 } {
#@   setenv LMC_HOME ""
#@ }
#@ 
#@ 
#@ #
#@ #
#@ #       Site-Specific Variables
#@ #
#@ #       These are the variables that are most commonly changed at a
#@ #       specific site, either upon installation of the Synopsys software,
#@ #       or by specific engineers in their local .synopsys files.
#@ #
#@ #
#@ 
#@ # from the System Variable Group 
#@ set link_force_case  "check_reference"
#@ set link_library  { * your_library.db }
#@ set physical_library ""
#@ 
#@ set search_path [list . ${synopsys_root}/libraries/syn ${synopsys_root}/dw/sim_ver]
#@ set target_library  your_library.db
#@ set synthetic_library  ""
#@ set command_log_file  "./command.log"
#@ set designer  ""
#@ set company  ""
#@ set find_converts_name_lists  "false"
#@ 
#@ set symbol_library  your_library.sdb 
#@ 
#@ # from the Schematic Variable Group 
#@ 
#@ # from the Plot Variable Group 
#@ if { $sh_arch == "hp700" } {
#@   set plot_command "lp -d" 
#@ } else {
#@   set plot_command "lpr -Plw" 
#@ }
#@ 
#@ set view_command_log_file  "./view_command.log"
#@ 
#@ # from the View Variable group
#@ if { $sh_arch == "hp700" } {
#@    set text_print_command  "lp -d" 
#@ } else {
#@    set text_print_command  "lpr -Plw" 
#@ }
#@ #
#@ #       System Variable Group:
#@ #
#@ #       These variables are system-wide variables.
#@ #
#@ set arch_init_path ${synopsys_root}/${sh_arch}/motif/syn/uid
#@ set auto_link_disable  "false"
#@ set auto_link_options  "-all"
#@ set uniquify_naming_style  "%s_%d"
#@ set verbose_messages  "true"
#@ set echo_include_commands  "true"
#@ set preserve_subshells  "hdl_shell_exec"
#@ set suppress_errors  {PWR-18 OPT-932}
#@ set change_names_update_inst_tree   "true"
#@ set change_names_dont_change_bus_members false
#@ set default_name_rules ""
#@ 
#@ #
#@ #       Compile Variable Group:
#@ #
#@ #       These variables affect the designs created by the COMPILE command.
#@ #
#@ set compile_assume_fully_decoded_three_state_busses   "false"
#@ set compile_automatic_clock_phase_inference    "strict"
#@ set compile_no_new_cells_at_top_level   "false"
#@ set compile_dont_touch_annotated_cell_during_inplace_opt   "false"
#@ set compile_update_annotated_delays_during_inplace_opt  "true"
#@ set compile_instance_name_prefix   "U"
#@ set compile_instance_name_suffix   ""
#@ set compile_negative_logic_methodology   "false"
#@ set compile_disable_hierarchical_inverter_opt   "false"
#@ set compile_use_fast_delay_mode   "true"
#@ set compile_use_low_timing_effort   "false"
#@ set compile_new_boolean_structure   "false"
#@ set compile_fix_cell_degradation   "false"
#@ set compile_preserve_subdesign_interfaces   "false"
#@ set compile_sequential_area_recovery   "false"
#@ set port_complement_naming_style   "%s_BAR"
#@ set compile_implementation_selection   "true"
#@ set compile_mux_no_boundary_optimization   "false"
#@ set compile_create_mux_op_hierarchy   "true"
#@ set compile_delete_unloaded_sequential_cells   "true"
#@ set reoptimize_design_changed_list_file_name   ""
#@ set compile_checkpoint_filename "./CHECKPOINT.db"
#@ set compile_checkpoint_cpu_interval 0.0
#@ set compile_checkpoint_phases "false"
#@ set compile_checkpoint_pre_delay_filename "./CHECKPOINT_PRE_DELAY.db"
#@ set compile_checkpoint_pre_drc1_filename "./CHECKPOINT_PRE_DRC1.db"
#@ set compile_checkpoint_pre_drc2_filename "./CHECKPOINT_PRE_DRC2.db"
#@ set compile_checkpoint_pre_area_filename "./CHECKPOINT_PRE_AREA.db"
#@ set compile_cpu_limit 0.0
#@ set compile_log_format "  %elap_time %area %wns %tns %drc %endpoint";
#@ set compile_top_all_paths   "false"
#@ set default_port_connection_class "universal"
#@ set compile_dw_simple_mode "false"
#@ set compile_simple_mode_block_effort "none"
#@ set compile_hold_reduce_cell_count "false"
#@ set compile_new_optimization "false"
#@ 
#@ 
#@ set ldd_return_val 0
#@ if { [string compare $dc_shell_mode "default"] == 0 } {
#@   set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.dcsh
#@   alias list_duplicate_designs "include -quiet ldd_script; dc_shell_status = ldd_return_val "
#@ 
#@ }
#@ if { [string compare $dc_shell_mode "tcl"] == 0 } {
#@   set ldd_script ${synopsys_root}/auxx/syn/scripts/list_duplicate_designs.tcl
#@   alias list_duplicate_designs "source $ldd_script; set dc_shell_status $ldd_return_val "
#@ }
#@ 
#@ 
#@ set compile_log_format "  %elap_time %area %wns %tns %drc %endpoint";
#@ 
#@ set compile_top_all_paths "false"
#@ alias compile_inplace_changed_list_file_name                 reoptimize_design_changed_list_file_name
#@ #
#@ #  These variables affects compile, report_timing and report_constraints
#@ #  commands.
#@ #
#@ set enable_recovery_removal_arcs  "false"
#@ 
#@ #
#@ #       Multibit Variable Group:
#@ #
#@ #       These variables affect the multibit mapping functionality
#@ #
#@ 
#@ set bus_multiple_separator_style  ","
#@ 
#@ #
#@ #       Estimator Variable Group:
#@ #
#@ #       These variables affect the designs created by the ESTIMATE command.
#@ #
#@ set estimate_resource_preference  "fast"
#@ alias est_resource_preference estimate_resource_preference
#@ set lbo_lfo_enable_at_pin_count   3
#@ set lbo_cells_in_regions   "false"
#@ 
#@ #     Synthetic Library Group:
#@ #
#@ #       These variable affect synthetic library processing.
#@ #
#@ set cache_dir_chmod_octal   "777"
#@ set cache_file_chmod_octal  "666"
#@ set cache_read   "~"
#@ set cache_read_info  "false"
#@ set cache_write  "~"
#@ set cache_write_info   "false"
#@ set dw_prefer_mc_inside "false"
#@ set mgi_scratch_directory "designware_generator"
#@ set synlib_disable_limited_licenses   "true"
#@ set synlib_dont_get_license  {}
#@ set synlib_evaluation_mode  "false"
#@ set synlib_library_list   {DW01 DW02 DW03 DW04 DW05 DW06 DW07 DW08}
#@ set synlib_model_map_effort  "medium"
#@ set synlib_optimize_non_cache_elements  "true"
#@ set synlib_prefer_ultra_license "false"
#@ set synlib_sequential_module   "default"
#@ set synlib_wait_for_design_license {}
#@ 
#@ #
#@ #       Insert_DFT Variable Group:
#@ #
#@ set test_default_client_order [list]
#@ set test_point_keep_hierarchy "false" 
#@ set insert_dft_clean_up "true"
#@ 
#@ #
#@ #       Insert_Test Variable Group:
#@ #
#@ #       These variables affect the designs created by the INSERT_TEST and INSERT_SCAN commands.
#@ #
#@ set insert_test_design_naming_style  "%s_test_%d"
#@ # /*insert_test_scan_chain_only_one_clock = "false"
#@ # Replace by command line option (star 17215) -- Denis Martin 28-Jan-93*/
#@ set test_clock_port_naming_style  "test_c%s"
#@ set test_scan_clock_a_port_naming_style  "test_sca%s"
#@ set test_scan_clock_b_port_naming_style  "test_scb%s"
#@ set test_scan_clock_port_naming_style   "test_sc%s"
#@ set test_scan_enable_inverted_port_naming_style   "test_sei%s"
#@ set test_scan_enable_port_naming_style   "test_se%s"
#@ set test_scan_in_port_naming_style   "test_si%s%s"
#@ set test_scan_out_port_naming_style  "test_so%s%s"
#@ set test_non_scan_clock_port_naming_style  "test_nsc_%s"
#@ set test_default_min_fault_coverage  95
#@ set insert_test_map_effort_enabled  TRUE
#@ set test_dedicated_subdesign_scan_outs  "true"
#@ set test_disable_find_best_scan_out  "false"
#@ set test_dont_fix_constraint_violations  "false"
#@ set test_isolate_hier_scan_out  0
#@ set test_mode_port_naming_style  "test_mode%s"
#@ set test_mode_port_inverted_naming_style  "test_mode_i%s"
#@ set compile_dont_use_dedicated_scanout 1
#@ 
#@ #
#@ #        Analyze_Scan Variable Group:
#@ #
#@ #     These variables affect the designs created by the PREVIEW_SCAN command.
#@ #
#@ set test_preview_scan_shows_cell_types  "false"
#@ set test_scan_link_so_lockup_key "l"
#@ set test_scan_link_wire_key  "w"
#@ set test_scan_segment_key  "s"
#@ set test_scan_true_key  "t"
#@ set test_jump_over_bufs_invs "true"
#@ 
#@ #
#@ #        bsd Variable Group:
#@ 
#@ #        These variables affect the report generated by the check_bsd command
#@ #        and the BSDLout generated by the write_bsdl command.
#@ #
#@ set test_user_test_data_register_naming_style  "UTDR%d"
#@ 
#@ set test_user_defined_instruction_naming_style  "USER%d"
#@ 
#@ set test_bsdl_default_suffix_name  "bsdl"
#@ 
#@ set test_bsdl_max_line_length  80
#@ 
#@ set test_cc_ir_masked_bits 0
#@ 
#@ set test_cc_ir_value_of_masked_bits 0
#@ 
#@ set test_bsd_allow_tolerable_violations "false" 
#@ set test_bsd_optimize_control_cell "false" 
#@ set test_bsd_control_cell_drive_limit 0
#@ set test_bsd_manufacturer_id 0
#@ set test_bsd_part_number 0
#@ set test_bsd_version_number 0
#@ 
#@ 
#@ #
#@ #        TestManager Variable Group:
#@ #
#@ #        These variables affect the TestManager methodology.
#@ #
#@ set multi_pass_test_generation  "false"
#@ 
#@ #
#@ #        TestSim Variable Group:
#@ #
#@ #        These variables affect the TestSim behavior.
#@ #
#@ # set testsim_print_stats_file  "true"
#@ 
#@ #      Test DRC Variable Group:
#@ #
#@ #        These variables affect the check_test command.
#@ # 
#@ set test_capture_clock_skew  "small_skew"
#@ set test_allow_clock_reconvergence  "true"
#@ set test_check_port_changes_in_capture  "true"
#@ set test_infer_slave_clock_pulse_after_capture "infer"
#@ 
#@ #
#@ #       Test Variable Group:
#@ #
#@ #       These variables affect the rtldrc, check_test, write_test_protocol
#@ #       and write_test command.
#@ #
#@ set test_default_delay  5.0
#@ set test_default_bidir_delay  55.0
#@ set test_default_strobe  95.0
#@ set test_default_strobe_width  0.0
#@ set test_default_period  100.0
#@ set test_default_scan_style  "multiplexed_flip_flop"
#@ set test_stil_netlist_format "db"
#@ set test_stil_multiclock_capture_procedures "false"
#@ set test_stil_max_line_length 72 
#@ set test_write_four_cycle_stil_protocol "false"
#@ set test_protocol_add_cycle "true"
#@ set test_rtldrc_latch_check_style "default"
#@ 
#@ #
#@ #       JTAG variable group (associated with the insert_jtag command):
#@ #
#@ #       These variables are associated with JTAG synthesis.
#@ #