time_sim.vhd

台湾全华科技VHDL教材实例

    );
  SYN724_FGBLOCK_LUTRAM_FLUT_AND0_22 : X_AND2 
    port map (
      I0 => INPUTDIGIT(0, 2),
      I1 => SYN724_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN724_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN724_FGBLOCK_LUTRAM_FLUT_AND1_23 : X_AND2 
    port map (
      I0 => SYN724_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(0, 2),
      O => SYN724_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN724_FGBLOCK_LUTRAM_FLUT_AND2_24 : X_AND2 
    port map (
      I0 => SYN724_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN724_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN724_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN724_FGBLOCK_LUTRAM_FLUT_AND3_25 : X_AND2 
    port map (
      I0 => INPUTDIGIT(0, 3),
      I1 => SYN724_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN724_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN724_FGBLOCK_LUTRAM_FLUT_AND4_26 : X_AND2 
    port map (
      I0 => SYN724_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(0, 3),
      O => SYN724_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN724_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN724_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN724_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN724_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN724_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN723_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN723_F,
      O => SYN723
    );
  SYN723_FGBLOCK_LUTRAM_FLUT_AND0_27 : X_AND2 
    port map (
      I0 => INPUTDIGIT(0, 0),
      I1 => SYN723_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN723_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN723_FGBLOCK_LUTRAM_FLUT_AND1_28 : X_AND2 
    port map (
      I0 => SYN723_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(0, 0),
      O => SYN723_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN723_FGBLOCK_LUTRAM_FLUT_AND2_29 : X_AND2 
    port map (
      I0 => SYN723_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN723_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN723_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN723_FGBLOCK_LUTRAM_FLUT_AND3_30 : X_AND2 
    port map (
      I0 => INPUTDIGIT(0, 1),
      I1 => SYN723_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN723_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN723_FGBLOCK_LUTRAM_FLUT_AND4_31 : X_AND2 
    port map (
      I0 => SYN723_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(0, 1),
      O => SYN723_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN723_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN723_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN723_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN723_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN723_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN722_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN722_F,
      O => SYN722
    );
  SYN722_FGBLOCK_LUTRAM_FLUT_AND0_32 : X_AND2 
    port map (
      I0 => INPUTDIGIT(1, 2),
      I1 => SYN722_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN722_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN722_FGBLOCK_LUTRAM_FLUT_AND1_33 : X_AND2 
    port map (
      I0 => SYN722_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(1, 2),
      O => SYN722_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN722_FGBLOCK_LUTRAM_FLUT_AND2_34 : X_AND2 
    port map (
      I0 => SYN722_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN722_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN722_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN722_FGBLOCK_LUTRAM_FLUT_AND3_35 : X_AND2 
    port map (
      I0 => INPUTDIGIT(1, 3),
      I1 => SYN722_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN722_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN722_FGBLOCK_LUTRAM_FLUT_AND4_36 : X_AND2 
    port map (
      I0 => SYN722_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(1, 3),
      O => SYN722_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN722_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN722_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN722_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN722_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN722_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN721_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN721_F,
      O => SYN721
    );
  SYN721_FGBLOCK_LUTRAM_FLUT_AND0_37 : X_AND2 
    port map (
      I0 => INPUTDIGIT(1, 0),
      I1 => SYN721_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN721_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN721_FGBLOCK_LUTRAM_FLUT_AND1_38 : X_AND2 
    port map (
      I0 => SYN721_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(1, 0),
      O => SYN721_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN721_FGBLOCK_LUTRAM_FLUT_AND2_39 : X_AND2 
    port map (
      I0 => SYN721_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN721_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN721_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN721_FGBLOCK_LUTRAM_FLUT_AND3_40 : X_AND2 
    port map (
      I0 => INPUTDIGIT(1, 1),
      I1 => SYN721_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN721_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN721_FGBLOCK_LUTRAM_FLUT_AND4_41 : X_AND2 
    port map (
      I0 => SYN721_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(1, 1),
      O => SYN721_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN721_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN721_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN721_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN721_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN721_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN720_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN720_F,
      O => SYN720
    );
  SYN720_FGBLOCK_LUTRAM_FLUT_AND0_42 : X_AND2 
    port map (
      I0 => INPUTDIGIT(2, 2),
      I1 => SYN720_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN720_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN720_FGBLOCK_LUTRAM_FLUT_AND1_43 : X_AND2 
    port map (
      I0 => SYN720_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(2, 2),
      O => SYN720_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN720_FGBLOCK_LUTRAM_FLUT_AND2_44 : X_AND2 
    port map (
      I0 => SYN720_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN720_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN720_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN720_FGBLOCK_LUTRAM_FLUT_AND3_45 : X_AND2 
    port map (
      I0 => INPUTDIGIT(2, 3),
      I1 => SYN720_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN720_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN720_FGBLOCK_LUTRAM_FLUT_AND4_46 : X_AND2 
    port map (
      I0 => SYN720_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(2, 3),
      O => SYN720_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN720_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN720_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN720_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN720_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN720_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN719_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN719_F,
      O => SYN719
    );
  SYN719_FGBLOCK_LUTRAM_FLUT_AND0_47 : X_AND2 
    port map (
      I0 => INPUTDIGIT(2, 0),
      I1 => SYN719_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN719_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN719_FGBLOCK_LUTRAM_FLUT_AND1_48 : X_AND2 
    port map (
      I0 => SYN719_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(2, 0),
      O => SYN719_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN719_FGBLOCK_LUTRAM_FLUT_AND2_49 : X_AND2 
    port map (
      I0 => SYN719_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN719_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN719_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN719_FGBLOCK_LUTRAM_FLUT_AND3_50 : X_AND2 
    port map (
      I0 => INPUTDIGIT(2, 1),
      I1 => SYN719_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN719_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN719_FGBLOCK_LUTRAM_FLUT_AND4_51 : X_AND2 
    port map (
      I0 => SYN719_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(2, 1),
      O => SYN719_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN719_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN719_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN719_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN719_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN719_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN718_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN718_F,
      O => SYN718
    );
  SYN718_FGBLOCK_LUTRAM_FLUT_AND0_52 : X_AND2 
    port map (
      I0 => INPUTDIGIT(3, 2),
      I1 => SYN718_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN718_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN718_FGBLOCK_LUTRAM_FLUT_AND1_53 : X_AND2 
    port map (
      I0 => SYN718_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(3, 2),
      O => SYN718_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN718_FGBLOCK_LUTRAM_FLUT_AND2_54 : X_AND2 
    port map (
      I0 => SYN718_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => SYN718_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => SYN718_FGBLOCK_LUTRAM_FLUT_AND2
    );
  SYN718_FGBLOCK_LUTRAM_FLUT_AND3_55 : X_AND2 
    port map (
      I0 => INPUTDIGIT(3, 3),
      I1 => SYN718_FGBLOCK_LUTRAM_FLUT_AND3_1_INV,
      O => SYN718_FGBLOCK_LUTRAM_FLUT_AND3
    );
  SYN718_FGBLOCK_LUTRAM_FLUT_AND4_56 : X_AND2 
    port map (
      I0 => SYN718_FGBLOCK_LUTRAM_FLUT_AND4_0_INV,
      I1 => LARRAY(3, 3),
      O => SYN718_FGBLOCK_LUTRAM_FLUT_AND4
    );
  SYN718_FGBLOCK_LUTRAM_FLUT_AND5 : X_AND3 
    port map (
      I0 => SYN718_FGBLOCK_LUTRAM_FLUT_AND2,
      I1 => SYN718_FGBLOCK_LUTRAM_FLUT_AND5_1_INV,
      I2 => SYN718_FGBLOCK_LUTRAM_FLUT_AND5_2_INV,
      O => SYN718_FGBLOCK_LUTRAM_FLUT_AND5_3_INV
    );
  SYN717_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN717_F,
      O => SYN717
    );
  SYN717_FGBLOCK_LUTRAM_FLUT_AND0_57 : X_AND2 
    port map (
      I0 => INPUTDIGIT(3, 0),
      I1 => SYN717_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN717_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN717_FGBLOCK_LUTRAM_FLUT_AND1_58 : X_AND2 
    port map (
      I0 => SYN717_FGBLOCK_LUTRAM_FLUT_AND1_0_INV,
      I1 => LARRAY(3, 0),
      O => SYN717_FGBLOCK_LUTRAM_FLUT_AND1
    );
  SYN717_FGBLOCK_LUTRAM_FLUT_AND2_5