time_sim.vhd

来自「台湾全华科技VHDL教材实例」· VHDL 代码 · 共 1,544 行 · 第 1/5 页

  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND5_3_INV : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND5_3_INV : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND5_3_INV : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND5_3_INV : STD_LOGIC; 
  signal N357_DFF_OUT_LATCHY_LATCH_1_INV : STD_LOGIC; 
  signal N357_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal N357_FGBLOCK_LUTRAM_GLUT_AND1_2_INV : STD_LOGIC; 
  signal INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_1_INV : STD_LOGIC; 
  signal INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_2_INV : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_FLUT_AND2_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_GLUT_AND1_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_GLUT_AND2_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_GLUT_AND2_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_FLUT_AND2_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_GLUT_AND1_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_GLUT_AND2_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_GLUT_AND2_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal NMATCH_OUTBLOCK_OUT_BUF_GTS_TRI_2_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_1_INV : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND2_2_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND3_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND3_1_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND4_0_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND5_1_INV : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND5_2_INV : STD_LOGIC; 
  signal PRESENTSTATE_0_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal PRESENTSTATE_0_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; 
  signal PRESENTSTATE_0_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal PRESENTSTATE_0_FGBLOCK_LUTRAM_FLUT_AND2_2_INV : STD_LOGIC; 
  signal PRESENTSTATE_0_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal PRESENTSTATE_2_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal N_IND : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal PINCNT : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal LARRAY : STD_LOGIC_VECTOR2 ( 3 downto 0 , 3 downto 0 ); 
  signal PRESENTSTATE : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal INPUTCNT : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal INPUTDIGIT : STD_LOGIC_VECTOR2 ( 3 downto 0 , 3 downto 0 ); 
begin
  C609 : X_CKBUF 
    port map (
      I => CLK_INT,
      O => CLK_BUFGED
    );
  C610 : X_CKBUF 
    port map (
      I => N379,
      O => N379_BUFGED
    );
  N_440_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N_440_G,
      O => C6_N51
    );
  N_440_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N_440_F,
      O => N_440
    );
  N_440_FGBLOCK_LUTRAM_FLUT_AND0 : X_AND2 
    port map (
      I0 => N_440_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => N_440_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => N_440_F
    );
  N_440_FGBLOCK_LUTRAM_GLUT_AND0_0 : X_AND2 
    port map (
      I0 => N_440_FGBLOCK_LUTRAM_GLUT_AND0_0_INV,
      I1 => N_440_FGBLOCK_LUTRAM_GLUT_AND0_1_INV,
      O => N_440_FGBLOCK_LUTRAM_GLUT_AND0
    );
  N_440_FGBLOCK_LUTRAM_GLUT_AND1_1 : X_AND2 
    port map (
      I0 => N_440_FGBLOCK_LUTRAM_GLUT_AND1_0_INV,
      I1 => N_440_FGBLOCK_LUTRAM_GLUT_AND1_1_INV,
      O => N_440_FGBLOCK_LUTRAM_GLUT_AND1
    );
  N_440_FGBLOCK_LUTRAM_GLUT_AND2 : X_AND2 
    port map (
      I0 => N_440_FGBLOCK_LUTRAM_GLUT_AND1,
      I1 => N_440_FGBLOCK_LUTRAM_GLUT_AND2_1_INV,
      O => N_440_FGBLOCK_LUTRAM_GLUT_AND2_2_INV
    );
  N363_DFF_OUT_XMUX : X_INV 
    port map (
      I => N_RSTPIN,
      O => N363
    );