time_sim.vhd

台湾全华科技VHDL教材实例

  N224_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N224_G,
      O => SYN438
    );
  N224_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N224_F,
      O => N224
    );
  N224_FGBLOCK_LUTRAM_FLUT_AND0_2 : X_AND2 
    port map (
      I0 => N224_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => SYN439,
      O => N224_FGBLOCK_LUTRAM_FLUT_AND0
    );
  N224_FGBLOCK_LUTRAM_FLUT_AND1 : X_AND3 
    port map (
      I0 => N224_FGBLOCK_LUTRAM_FLUT_AND0,
      I1 => PRESENTSTATE(1),
      I2 => N224_FGBLOCK_LUTRAM_FLUT_AND1_2_INV,
      O => N224_F
    );
  N224_FGBLOCK_LUTRAM_GLUT_AND0_3 : X_AND2 
    port map (
      I0 => SYN439,
      I1 => N224_FGBLOCK_LUTRAM_GLUT_AND0_1_INV,
      O => N224_FGBLOCK_LUTRAM_GLUT_AND0
    );
  N224_FGBLOCK_LUTRAM_GLUT_AND1 : X_AND2 
    port map (
      I0 => N224_FGBLOCK_LUTRAM_GLUT_AND0,
      I1 => PRESENTSTATE(2),
      O => N224_G
    );
  N1254_SR_4 : X_BUF 
    port map (
      I => N357,
      O => N1254_SR
    );
  N1254_DIN_5 : X_BUF 
    port map (
      I => PRESENTSTATE(3),
      O => N1254_DIN
    );
  N1254_DFF_OUT_DFFX : X_FF 
    port map (
      I => N1254_DIN,
      CLK => CLK_BUFGED,
      CE => C6_N51,
      SET => GND,
      RST => N1254_DFF_OUT_DFFX_GSR_OR,
      O => N1254_DFF_OUT_QXDFF
    );
  N1254_DFF_OUT_YMUX : X_BUF 
    port map (
      I => N1254_G,
      O => N379
    );
  N1254_DFF_OUT_XQMUX : X_BUF 
    port map (
      I => N1254_DFF_OUT_QXDFF,
      O => PRESENTSTATE(4)
    );
  N1254_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N1254_F,
      O => N1254
    );
  N1254_DFF_OUT_DFFX_GSR_OR_6 : X_OR2 
    port map (
      I0 => N1254_SR,
      I1 => GSR,
      O => N1254_DFF_OUT_DFFX_GSR_OR
    );
  N1254_FGBLOCK_LUTRAM_FLUT_AND0 : X_AND2 
    port map (
      I0 => N1254_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => N_RESET,
      O => N1254_FGBLOCK_LUTRAM_FLUT_AND0_2_INV
    );
  N1254_FGBLOCK_LUTRAM_GLUT_AND0_7 : X_AND2 
    port map (
      I0 => N_RESET,
      I1 => N1254_FGBLOCK_LUTRAM_GLUT_AND0_1_INV,
      O => N1254_FGBLOCK_LUTRAM_GLUT_AND0
    );
  N1254_FGBLOCK_LUTRAM_GLUT_AND1 : X_AND2 
    port map (
      I0 => N1254_FGBLOCK_LUTRAM_GLUT_AND0,
      I1 => N1254_FGBLOCK_LUTRAM_GLUT_AND1_1_INV,
      O => N1254_G
    );
  C17_N80_DFF_OUT_YMUX : X_BUF 
    port map (
      I => C17_N80_G,
      O => SYN462
    );
  C17_N80_DFF_OUT_XMUX : X_BUF 
    port map (
      I => C17_N80_F,
      O => C17_N80
    );
  C17_N80_FGBLOCK_LUTRAM_FLUT_AND0_8 : X_AND2 
    port map (
      I0 => N352,
      I1 => N_RESET,
      O => C17_N80_FGBLOCK_LUTRAM_FLUT_AND0
    );
  C17_N80_FGBLOCK_LUTRAM_FLUT_AND1 : X_AND2 
    port map (
      I0 => C17_N80_FGBLOCK_LUTRAM_FLUT_AND0,
      I1 => C17_N80_FGBLOCK_LUTRAM_FLUT_AND1_1_INV,
      O => C17_N80_F
    );
  C17_N80_FGBLOCK_LUTRAM_GLUT_AND0_9 : X_AND2 
    port map (
      I0 => PRESENTSTATE(0),
      I1 => C17_N80_FGBLOCK_LUTRAM_GLUT_AND0_1_INV,
      O => C17_N80_FGBLOCK_LUTRAM_GLUT_AND0
    );
  C17_N80_FGBLOCK_LUTRAM_GLUT_AND1_10 : X_AND2 
    port map (
      I0 => PRESENTSTATE(0),
      I1 => C17_N80_FGBLOCK_LUTRAM_GLUT_AND1_1_INV,
      O => C17_N80_FGBLOCK_LUTRAM_GLUT_AND1
    );
  C17_N80_FGBLOCK_LUTRAM_GLUT_AND2 : X_AND2 
    port map (
      I0 => C17_N80_FGBLOCK_LUTRAM_GLUT_AND2_0_INV,
      I1 => C17_N80_FGBLOCK_LUTRAM_GLUT_AND2_1_INV,
      O => C17_N80_FGBLOCK_LUTRAM_GLUT_AND2_2_INV
    );
  N352_SR_11 : X_BUF 
    port map (
      I => N357,
      O => N352_SR
    );
  N352_H1_12 : X_BUF 
    port map (
      I => INPUTCNT(2),
      O => N352_H1
    );
  N352_DFF_OUT_DFFY : X_FF 
    port map (
      I => N352_G,
      CLK => N352_DFF_OUT_DFFY_1_INV,
      CE => VCC,
      SET => N352_DFF_OUT_DFFY_GSR_OR,
      RST => GND,
      O => N352_DFF_OUT_QYDFF
    );
  N352_DFF_OUT_YQMUX : X_BUF 
    port map (
      I => N352_DFF_OUT_QYDFF,
      O => NMATCHI1
    );
  N352_DFF_OUT_XMUX : X_BUF 
    port map (
      I => N352_H,
      O => N352
    );
  N352_DFF_OUT_DFFY_GSR_OR_13 : X_OR2 
    port map (
      I0 => N352_SR,
      I1 => GSR,
      O => N352_DFF_OUT_DFFY_GSR_OR
    );
  N352_FGBLOCK_LUTRAM_FLUT_AND0_14 : X_AND2 
    port map (
      I0 => SYN457,
      I1 => PRESENTSTATE(3),
      O => N352_FGBLOCK_LUTRAM_FLUT_AND0
    );
  N352_FGBLOCK_LUTRAM_FLUT_AND1_15 : X_AND2 
    port map (
      I0 => N352_FGBLOCK_LUTRAM_FLUT_AND0,
      I1 => N352_FGBLOCK_LUTRAM_FLUT_AND1_1_INV,
      O => N352_FGBLOCK_LUTRAM_FLUT_AND1
    );
  N352_FGBLOCK_LUTRAM_FLUT_AND2 : X_AND2 
    port map (
      I0 => N352_FGBLOCK_LUTRAM_FLUT_AND2_0_INV,
      I1 => N352_FGBLOCK_LUTRAM_FLUT_AND2_1_INV,
      O => N352_FGBLOCK_LUTRAM_FLUT_AND2_2_INV
    );
  N352_FGBLOCK_LUTRAM_GLUT_AND0_16 : X_AND2 
    port map (
      I0 => N352_FGBLOCK_LUTRAM_GLUT_AND0_0_INV,
      I1 => SYN438,
      O => N352_FGBLOCK_LUTRAM_GLUT_AND0
    );
  N352_FGBLOCK_LUTRAM_GLUT_AND1 : X_AND3 
    port map (
      I0 => N352_FGBLOCK_LUTRAM_GLUT_AND0,
      I1 => CELL224,
      I2 => INPUTCNT(2),
      O => N352_FGBLOCK_LUTRAM_GLUT_AND1_3_INV
    );
  N352_HLUT_AND0 : X_AND2 
    port map (
      I0 => N352_HLUT_AND0_0_INV,
      I1 => N352_F,
      O => N352_H
    );
  CELL224_DFF_OUT_YMUX : X_BUF 
    port map (
      I => CELL224_G,
      O => SYN464
    );
  CELL224_DFF_OUT_XMUX : X_BUF 
    port map (
      I => CELL224_F,
      O => CELL224
    );
  CELL224_FGBLOCK_LUTRAM_FLUT_AND0 : X_AND2 
    port map (
      I0 => CELL224_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => CELL224_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => CELL224_F
    );
  CELL224_FGBLOCK_LUTRAM_GLUT_AND0_17 : X_AND2 
    port map (
      I0 => PRESENTSTATE(3),
      I1 => INPUTCNT(1),
      O => CELL224_FGBLOCK_LUTRAM_GLUT_AND0
    );
  CELL224_FGBLOCK_LUTRAM_GLUT_AND1 : X_AND3 
    port map (
      I0 => CELL224_FGBLOCK_LUTRAM_GLUT_AND0,
      I1 => CELL224_FGBLOCK_LUTRAM_GLUT_AND1_1_INV,
      I2 => INPUTCNT(0),
      O => CELL224_G
    );
  SYN439_DFF_OUT_YMUX : X_BUF 
    port map (
      I => SYN439_G,
      O => SYN457
    );
  SYN439_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN439_F,
      O => SYN439
    );
  SYN439_FGBLOCK_LUTRAM_FLUT_AND0_18 : X_AND2 
    port map (
      I0 => SYN439_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => SYN439_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN439_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN439_FGBLOCK_LUTRAM_FLUT_AND1 : X_AND2 
    port map (
      I0 => SYN439_FGBLOCK_LUTRAM_FLUT_AND0,
      I1 => SYN439_FGBLOCK_LUTRAM_FLUT_AND1_1_INV,
      O => SYN439_F
    );
  SYN439_FGBLOCK_LUTRAM_GLUT_AND0_19 : X_AND2 
    port map (
      I0 => SYN439_FGBLOCK_LUTRAM_GLUT_AND0_0_INV,
      I1 => SYN439_FGBLOCK_LUTRAM_GLUT_AND0_1_INV,
      O => SYN439_FGBLOCK_LUTRAM_GLUT_AND0
    );
  SYN439_FGBLOCK_LUTRAM_GLUT_AND1 : X_AND2 
    port map (
      I0 => SYN439_FGBLOCK_LUTRAM_GLUT_AND0,
      I1 => SYN439_FGBLOCK_LUTRAM_GLUT_AND1_1_INV,
      O => SYN439_G
    );
  SYN530_DFF_OUT_YMUX : X_BUF 
    port map (
      I => SYN530_H,
      O => SYN530
    );
  SYN530_FGBLOCK_LUTRAM_FLUT_AND0_20 : X_AND2 
    port map (
      I0 => SYN530_FGBLOCK_LUTRAM_FLUT_AND0_0_INV,
      I1 => SYN530_FGBLOCK_LUTRAM_FLUT_AND0_1_INV,
      O => SYN530_FGBLOCK_LUTRAM_FLUT_AND0
    );
  SYN530_FGBLOCK_LUTRAM_FLUT_AND1 : X_AND3 
    port map (
      I0 => SYN530_FGBLOCK_LUTRAM_FLUT_AND0,
      I1 => SYN530_FGBLOCK_LUTRAM_FLUT_AND1_1_INV,
      I2 => SYN530_FGBLOCK_LUTRAM_FLUT_AND1_2_INV,
      O => SYN530_FGBLOCK_LUTRAM_FLUT_AND1_3_INV
    );
  SYN530_FGBLOCK_LUTRAM_GLUT_AND0_21 : X_AND2 
    port map (
      I0 => SYN530_FGBLOCK_LUTRAM_GLUT_AND0_0_INV,
      I1 => SYN530_FGBLOCK_LUTRAM_GLUT_AND0_1_INV,
      O => SYN530_FGBLOCK_LUTRAM_GLUT_AND0
    );
  SYN530_FGBLOCK_LUTRAM_GLUT_AND1 : X_AND3 
    port map (
      I0 => SYN530_FGBLOCK_LUTRAM_GLUT_AND0,
      I1 => SYN530_FGBLOCK_LUTRAM_GLUT_AND1_1_INV,
      I2 => SYN530_FGBLOCK_LUTRAM_GLUT_AND1_2_INV,
      O => SYN530_FGBLOCK_LUTRAM_GLUT_AND1_3_INV
    );
  SYN530_HLUT_AND0 : X_AND2 
    port map (
      I0 => SYN530_HLUT_AND0_0_INV,
      I1 => SYN530_HLUT_AND0_1_INV,
      O => SYN530_HLUT_AND0_2_INV
    );
  SYN724_DFF_OUT_XMUX : X_BUF 
    port map (
      I => SYN724_F,
      O => SYN724