time_sim.vhd

台湾全华科技VHDL教材实例

  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_F : STD_LOGIC; 
  signal INPUTDIGIT_2_2_G : STD_LOGIC; 
  signal INPUTDIGIT_2_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTDIGIT_2_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_2_2_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_F : STD_LOGIC; 
  signal INPUTDIGIT_3_0_G : STD_LOGIC; 
  signal INPUTDIGIT_3_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTDIGIT_3_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_3_0_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_F : STD_LOGIC; 
  signal INPUTDIGIT_3_2_G : STD_LOGIC; 
  signal INPUTDIGIT_3_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTDIGIT_3_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_3_2_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal NMATCH_OUTBLOCK_OUT_BUF_GTS_TRI : STD_LOGIC; 
  signal PINCNT_0_F : STD_LOGIC; 
  signal PINCNT_0_G : STD_LOGIC; 
  signal PINCNT_0_SR : STD_LOGIC; 
  signal PINCNT_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal PINCNT_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal PINCNT_0_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal PINCNT_0_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal PINCNT_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal PINCNT_2_F : STD_LOGIC; 
  signal PINCNT_2_SR : STD_LOGIC; 
  signal PINCNT_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal PINCNT_2_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal PINCNT_2_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal LARRAY_0_0_F : STD_LOGIC; 
  signal LARRAY_0_0_G : STD_LOGIC; 
  signal LARRAY_0_0_SR : STD_LOGIC; 
  signal LARRAY_0_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal LARRAY_0_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal LARRAY_0_0_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal LARRAY_0_0_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal LARRAY_0_0_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal LARRAY_0_2_F : STD_LOGIC; 
  signal LARRAY_0_2_G : STD_LOGIC; 
  signal LARRAY_0_2_SR : STD_LOGIC; 
  signal LARRAY_0_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal LARRAY_0_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal LARRAY_0_2_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal LARRAY_0_2_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal LARRAY_0_2_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal LARRAY_1_0_F : STD_LOGIC; 
  signal LARRAY_1_0_G : STD_LOGIC; 
  signal LARRAY_1_0_SR : STD_LOGIC; 
  signal LARRAY_1_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal LARRAY_1_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal LARRAY_1_0_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal LARRAY_1_0_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal LARRAY_1_0_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal LARRAY_1_2_F : STD_LOGIC; 
  signal LARRAY_1_2_G : STD_LOGIC; 
  signal LARRAY_1_2_SR : STD_LOGIC; 
  signal LARRAY_1_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal LARRAY_1_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal LARRAY_1_2_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal LARRAY_1_2_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal LARRAY_1_2_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal LARRAY_2_0_F : STD_LOGIC; 
  signal LARRAY_2_0_G : STD_LOGIC; 
  signal LARRAY_2_0_SR : STD_LOGIC; 
  signal LARRAY_2_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal LARRAY_2_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal LARRAY_2_0_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal LARRAY_2_0_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal LARRAY_2_0_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal LARRAY_2_2_F : STD_LOGIC; 
  signal LARRAY_2_2_G : STD_LOGIC; 
  signal LARRAY_2_2_SR : STD_LOGIC; 
  signal LARRAY_2_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal LARRAY_2_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal LARRAY_2_2_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal LARRAY_2_2_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal LARRAY_2_2_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal LARRAY_3_0_F : STD_LOGIC; 
  signal LARRAY_3_0_G : STD_LOGIC; 
  signal LARRAY_3_0_SR : STD_LOGIC; 
  signal LARRAY_3_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal LARRAY_3_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal LARRAY_3_0_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal LARRAY_3_0_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal LARRAY_3_0_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal LARRAY_3_2_F : STD_LOGIC; 
  signal LARRAY_3_2_G : STD_LOGIC; 
  signal LARRAY_3_2_SR : STD_LOGIC; 
  signal LARRAY_3_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal LARRAY_3_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal LARRAY_3_2_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal LARRAY_3_2_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal LARRAY_3_2_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal PRESENTSTATE_0_F : STD_LOGIC; 
  signal PRESENTSTATE_0_G : STD_LOGIC; 
  signal PRESENTSTATE_0_SR : STD_LOGIC; 
  signal PRESENTSTATE_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal PRESENTSTATE_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal PRESENTSTATE_0_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal PRESENTSTATE_0_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal PRESENTSTATE_0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal PRESENTSTATE_0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal PRESENTSTATE_2_F : STD_LOGIC; 
  signal PRESENTSTATE_2_G : STD_LOGIC; 
  signal PRESENTSTATE_2_SR : STD_LOGIC; 
  signal PRESENTSTATE_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal PRESENTSTATE_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal PRESENTSTATE_2_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal PRESENTSTATE_2_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal RESET_INBLOCK_I : STD_LOGIC; 
  signal RSTPIN_INBLOCK_I : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_GLUT_AND1_0_INV : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_GLUT_AND2_1_INV : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_GLUT_AND2_2_INV : STD_LOGIC; 
  signal N224_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal N224_FGBLOCK_LUTRAM_FLUT_AND1_2_INV : STD_LOGIC; 
  signal N224_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal N1254_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal N1254_FGBLOCK_LUTRAM_FLUT_AND0_2_INV : STD_LOGIC; 
  signal N1254_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal N1254_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal C17_N80_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; 
  signal C17_N80_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal C17_N80_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal C17_N80_FGBLOCK_LUTRAM_GLUT_AND2_0_INV : STD_LOGIC; 
  signal C17_N80_FGBLOCK_LUTRAM_GLUT_AND2_1_INV : STD_LOGIC; 
  signal C17_N80_FGBLOCK_LUTRAM_GLUT_AND2_2_INV : STD_LOGIC; 
  signal N352_DFF_OUT_DFFY_1_INV : STD_LOGIC; 
  signal N352_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; 
  signal N352_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal N352_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal N352_FGBLOCK_LUTRAM_FLUT_AND2_2_INV : STD_LOGIC; 
  signal N352_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal N352_FGBLOCK_LUTRAM_GLUT_AND1_3_INV : STD_LOGIC; 
  signal N352_HLUT_AND0_0_INV : STD_LOGIC; 
  signal CELL224_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal CELL224_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal CELL224_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal SYN439_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal SYN439_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN439_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; 
  signal SYN439_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal SYN439_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN439_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_FLUT_AND0_0_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_FLUT_AND1_1_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_FLUT_AND1_2_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_FLUT_AND1_3_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_GLUT_AND0_0_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_GLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_GLUT_AND1_1_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_GLUT_AND1_2_INV : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_GLUT_AND1_3_INV : STD_LOGIC; 
  signal SYN530_HLUT_AND0_0_INV : STD_LOGIC; 
  signal SYN530_HLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN530_HLUT_AND0_2_INV : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND5_3_INV : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND5_3_INV : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND5_3_INV : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND4_0_INV : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND5_1_INV : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND5_2_INV : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND5_3_INV : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND0_1_INV : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND1_0_INV : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND2_0_INV : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND2_1_INV : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND3_1_INV : STD_LOGIC;