time_sim.vhd

台湾全华科技VHDL教材实例

-- Xilinx Vhdl produced by program ngd2vhdl C.18
-- Command: -w PinCheck.nga time_sim.vhd 
-- Options: -w -ti UUT 
-- Date: Mon Jul 24 00:11:30 2000 
-- Input file: PinCheck.nga
-- Output file: time_sim.vhd
-- Tmp file: C:/WINDOWS/TEMP/xil_6
-- Design name: PinCheck
-- Xilinx: E:/fndtn
-- # of Entities: 1
-- Device: s05xlpc84-4

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

-- Model for  TOC (Tristate-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity TOC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 0 ns);
  port(O : out std_ulogic := '0');
  attribute VITAL_LEVEL0 of TOC : entity is TRUE;
end TOC;

architecture TOC_V of TOC is
attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    O <= '1';
    if (WIDTH <= 0 ns) then
       O <= '0';
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end TOC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity PINCHECK is 
  port (
    CLK : in STD_LOGIC := 'X'; 
    DENTER : in STD_LOGIC := 'X'; 
    INDATA : in STD_LOGIC := 'X'; 
    INPINN : in STD_LOGIC := 'X'; 
    NMATCH : out STD_LOGIC; 
    RESET : in STD_LOGIC := 'X'; 
    RSTPIN : in STD_LOGIC := 'X'; 
    IND : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end PINCHECK;

architecture STRUCTURE of PINCHECK is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  component TOC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 0 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal N379_BUFGED : STD_LOGIC; 
  signal NMATCHI : STD_LOGIC; 
  signal N_DENTER : STD_LOGIC; 
  signal N_440 : STD_LOGIC; 
  signal N_RSTPIN : STD_LOGIC; 
  signal N363 : STD_LOGIC; 
  signal SYN439 : STD_LOGIC; 
  signal N224 : STD_LOGIC; 
  signal N_RESET : STD_LOGIC; 
  signal N1254 : STD_LOGIC; 
  signal CELL224 : STD_LOGIC; 
  signal N352 : STD_LOGIC; 
  signal C17_N80 : STD_LOGIC; 
  signal SYN438 : STD_LOGIC; 
  signal SYN457 : STD_LOGIC; 
  signal NMATCHI1 : STD_LOGIC; 
  signal SYN530 : STD_LOGIC; 
  signal N_INPINN : STD_LOGIC; 
  signal SYN721 : STD_LOGIC; 
  signal SYN722 : STD_LOGIC; 
  signal SYN723 : STD_LOGIC; 
  signal SYN724 : STD_LOGIC; 
  signal SYN717 : STD_LOGIC; 
  signal SYN718 : STD_LOGIC; 
  signal SYN719 : STD_LOGIC; 
  signal SYN720 : STD_LOGIC; 
  signal SYN462 : STD_LOGIC; 
  signal SYN464 : STD_LOGIC; 
  signal C6_N51 : STD_LOGIC; 
  signal N_INDATA : STD_LOGIC; 
  signal N357 : STD_LOGIC; 
  signal N379 : STD_LOGIC; 
  signal CLK_BUFGED : STD_LOGIC; 
  signal CLK_INT : STD_LOGIC; 
  signal N_440_F : STD_LOGIC; 
  signal N_440_G : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal N_440_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal N224_F : STD_LOGIC; 
  signal N224_G : STD_LOGIC; 
  signal N224_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal N224_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal N1254_DIN : STD_LOGIC; 
  signal N1254_F : STD_LOGIC; 
  signal N1254_G : STD_LOGIC; 
  signal N1254_SR : STD_LOGIC; 
  signal N1254_DFF_OUT_QXDFF : STD_LOGIC; 
  signal N1254_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal N1254_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal C17_N80_F : STD_LOGIC; 
  signal C17_N80_G : STD_LOGIC; 
  signal C17_N80_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal C17_N80_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal C17_N80_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal N352_F : STD_LOGIC; 
  signal N352_G : STD_LOGIC; 
  signal N352_H1 : STD_LOGIC; 
  signal N352_SR : STD_LOGIC; 
  signal N352_H : STD_LOGIC; 
  signal N352_DFF_OUT_QYDFF : STD_LOGIC; 
  signal N352_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal N352_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal N352_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal N352_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal CELL224_F : STD_LOGIC; 
  signal CELL224_G : STD_LOGIC; 
  signal CELL224_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal SYN439_F : STD_LOGIC; 
  signal SYN439_G : STD_LOGIC; 
  signal SYN439_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN439_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal SYN530_F : STD_LOGIC; 
  signal SYN530_G : STD_LOGIC; 
  signal SYN530_H : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN530_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal SYN724_F : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal SYN724_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal SYN723_F : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal SYN723_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal SYN722_F : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal SYN722_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal SYN721_F : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal SYN721_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal SYN720_F : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal SYN720_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal SYN719_F : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal SYN719_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal SYN718_F : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal SYN718_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal SYN717_F : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal SYN717_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal N357_G : STD_LOGIC; 
  signal N357_DFF_OUT_QYLATCH : STD_LOGIC; 
  signal N357_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal DENTER_INBLOCK_I : STD_LOGIC; 
  signal IND_0_INBLOCK_I : STD_LOGIC; 
  signal IND_1_INBLOCK_I : STD_LOGIC; 
  signal IND_2_INBLOCK_I : STD_LOGIC; 
  signal IND_3_INBLOCK_I : STD_LOGIC; 
  signal INDATA_INBLOCK_I : STD_LOGIC; 
  signal INPINN_INBLOCK_I : STD_LOGIC; 
  signal INPUTCNT_0_F : STD_LOGIC; 
  signal INPUTCNT_0_G : STD_LOGIC; 
  signal INPUTCNT_0_SR : STD_LOGIC; 
  signal INPUTCNT_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTCNT_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal INPUTCNT_0_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal INPUTCNT_0_DFF_OUT_DFFX_GSR_OR : STD_LOGIC; 
  signal INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal INPUTCNT_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal INPUTCNT_2_F : STD_LOGIC; 
  signal INPUTCNT_2_SR : STD_LOGIC; 
  signal INPUTCNT_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTCNT_2_DFF_OUT_DFFY_GSR_OR : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal INPUTCNT_2_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_0_0_F : STD_LOGIC; 
  signal INPUTDIGIT_0_0_G : STD_LOGIC; 
  signal INPUTDIGIT_0_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTDIGIT_0_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_0_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_0_2_F : STD_LOGIC; 
  signal INPUTDIGIT_0_2_G : STD_LOGIC; 
  signal INPUTDIGIT_0_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTDIGIT_0_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_0_2_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_F : STD_LOGIC; 
  signal INPUTDIGIT_1_0_G : STD_LOGIC; 
  signal INPUTDIGIT_1_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTDIGIT_1_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_1_0_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_F : STD_LOGIC; 
  signal INPUTDIGIT_1_2_G : STD_LOGIC; 
  signal INPUTDIGIT_1_2_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTDIGIT_1_2_DFF_OUT_QXDFF : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_1_2_FGBLOCK_LUTRAM_GLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_2_0_F : STD_LOGIC; 
  signal INPUTDIGIT_2_0_G : STD_LOGIC; 
  signal INPUTDIGIT_2_0_DFF_OUT_QYDFF : STD_LOGIC; 
  signal INPUTDIGIT_2_0_DFF_OUT_QXDFF : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND2 : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND3 : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_FLUT_AND4 : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND0 : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND1 : STD_LOGIC; 
  signal INPUTDIGIT_2_0_FGBLOCK_LUTRAM_GLUT_AND2 : STD_LOGIC;