fct3805.vhd

来自「Vhdl cod for a clock for sp3e」· VHDL 代码 · 共 222 行

--------------------------------------------------------------------------------
--  File Name: fct3805.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1999-2002 Free Model Foundry; http://www.FreeModelFoundry.com/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Munden   99 APR 06   initial release
--    V2.0     R. Munden   02 APR 10   flattened model
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    CLOCK
--  Technology: CMOS
--  Part:       FCT3805
-- 
--  Description: Clock driver with 3-state outputs
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY fct3805 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_B                   : VitalDelayType01 := VitalZeroDelay01;
        tipd_OEANeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_OEBNeg              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_A_YA1                : VitalDelayType01  := UnitDelay01;
        tpd_B_YB1                : VitalDelayType01  := UnitDelay01;
        tpd_B_MON                : VitalDelayType01  := UnitDelay01;
        tpd_OEANeg_YA1           : VitalDelayType01Z  := UnitDelay01Z;
        tpd_OEBNeg_YB1           : VitalDelayType01Z  := UnitDelay01Z;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        YA1             : OUT   std_ulogic := 'U';
        YA2             : OUT   std_ulogic := 'U';
        YA3             : OUT   std_ulogic := 'U';
        YA4             : OUT   std_ulogic := 'U';
        YA5             : OUT   std_ulogic := 'U';
        YB1             : OUT   std_ulogic := 'U';
        YB2             : OUT   std_ulogic := 'U';
        YB3             : OUT   std_ulogic := 'U';
        YB4             : OUT   std_ulogic := 'U';
        YB5             : OUT   std_ulogic := 'U';
        MON             : OUT   std_ulogic := 'U';
        A               : IN    std_ulogic := 'U';
        B               : IN    std_ulogic := 'U';
        OEANeg          : IN    std_ulogic := 'U';
        OEBNeg          : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of fct3805 : ENTITY IS TRUE;
END fct3805;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of fct3805 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL A_ipd               : std_ulogic := 'U';
    SIGNAL B_ipd               : std_ulogic := 'U';
    SIGNAL OEANeg_ipd          : std_ulogic := 'U';
    SIGNAL OEBNeg_ipd          : std_ulogic := 'U';
    SIGNAL YA                  : std_ulogic := 'U';
    SIGNAL YB                  : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (A_ipd, A, tipd_A);
        w_2 : VitalWireDelay (B_ipd, B, tipd_B);
        w_3 : VitalWireDelay (OEANeg_ipd, OEANeg, tipd_OEANeg);
        w_4 : VitalWireDelay (OEBNeg_ipd, OEBNeg, tipd_OEBNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalIDENT (q => YA1, a => YA);
    a_2: VitalIDENT (q => YA2, a => YA);
    a_3: VitalIDENT (q => YA3, a => YA);
    a_4: VitalIDENT (q => YA4, a => YA);
    a_5: VitalIDENT (q => YA5, a => YA);
    a_6: VitalIDENT (q => YB1, a => YB);
    a_7: VitalIDENT (q => YB2, a => YB);
    a_8: VitalIDENT (q => YB3, a => YB);
    a_9: VitalIDENT (q => YB4, a => YB);
    a_10: VitalIDENT (q => YB5, a => YB);

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    VitalAOut : PROCESS (A_ipd, OEANeg_ipd)

        -- Functionality Results Variables
        VARIABLE YA_zd           : std_ulogic;
     
        -- Output Glitch Detection Variables
        VARIABLE YA_GlitchData   : VitalGlitchDataType;
 
    BEGIN
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        YA_zd := VitalBUFIF0 (data => A_ipd, enable => OEANeg_ipd);
 
        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       =>  YA,
            OutSignalName   =>  "YA",
            OutTemp         =>  YA_zd,
            GlitchData      => YA_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_A_YA1),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OEANeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_OEANeg_YA1,
                      PathCondition     => TRUE))
        );

    END PROCESS;
 
    VitalBOut : PROCESS (B_ipd, OEBNeg_ipd)

        -- Functionality Results Variables
        VARIABLE YB_zd           : std_ulogic;
     
        -- Output Glitch Detection Variables
        VARIABLE YB_GlitchData   : VitalGlitchDataType;
 
    BEGIN
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        YB_zd := VitalBUFIF0 (data => B_ipd, enable => OEBNeg_ipd);
 
        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       =>  YB,
            OutSignalName   =>  "YB",
            OutTemp         =>  YB_zd,
            GlitchData      => YB_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => B_ipd'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_B_YB1),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OEBNeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_OEBNeg_YB1,
                      PathCondition     => TRUE))
        );

    END PROCESS;
 
    VitalMon : PROCESS (B_ipd)

        -- Functionality Results Variables
        VARIABLE MON_zd           : std_ulogic;
     
        -- Output Glitch Detection Variables
        VARIABLE MON_GlitchData   : VitalGlitchDataType;
 
    BEGIN
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        MON_zd := VitalBUF (data => B_ipd);
 
        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       =>  MON,
            OutSignalName   =>  "MON",
            OutTemp         =>  MON_zd,
            GlitchData      => MON_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => B_ipd'LAST_EVENT,
                      PathDelay         => tpd_B_MON,
                      PathCondition     => TRUE))
        );

    END PROCESS;
 
END vhdl_behavioral;