cdc339.vhd

来自「Vhdl cod for a clock for sp3e」· VHDL 代码 · 共 282 行

--------------------------------------------------------------------------------
--  File Name: cdc339.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1997-2002 Free Model Foundry; http://www.FreeModelFoundry.com/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Munden   97 DEC 15   conforms to style guide
--    V1.1     R. Munden   98 APR 29   Removed unneeded generics
--    V1.2     R. Munden   02 MAR 29   Correct dummy pathdelay for ModelSim 5.6
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    CLOCK
--  Technology: TTL
--  Part:       CDC339
-- 
--  Desciption: Clock driver with 3-state outputs
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.ff_package.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY cdc339 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_CLK                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLRNeg              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_Y                : VitalDelayType01  := UnitDelay01;
        tpd_CLK_Q                : VitalDelayType01  := UnitDelay01;
        tpd_OENeg_Y              : VitalDelayType01Z := UnitDelay01Z;
        tpd_CLRNeg_Y             : VitalDelayType01  := UnitDelay01;
        -- tsetup values: setup times
        tsetup_CLRNeg_CLK        : VitalDelayType := UnitDelay;
        -- tpw values: pulse widths
        tpw_CLK_posedge     : VitalDelayType := UnitDelay;
        tpw_CLK_negedge     : VitalDelayType := UnitDelay;
        tpw_CLRNeg_negedge  : VitalDelayType := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLK_posedge : VitalDelayType := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        Y               : OUT   std_logic := 'U';
        Q               : OUT   std_logic := 'U';
        CLK             : IN    std_logic := 'U';
        OENeg           : IN    std_logic := 'U';
        CLRNeg          : IN    std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of cdc339 : ENTITY IS TRUE;
END cdc339;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of cdc339 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    SIGNAL CLK_ipd             : std_ulogic := 'X';
    SIGNAL OENeg_ipd           : std_ulogic := 'X';
    SIGNAL CLRNeg_ipd          : std_ulogic := 'X';
    SIGNAL CLRint              : std_ulogic := 'X';
    SIGNAL Tint                : std_ulogic := 'X';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_3 : VitalWireDelay (CLK_ipd, CLK, tipd_CLK);
        w_4 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_5 : VitalWireDelay (CLRNeg_ipd, CLRNeg, tipd_CLRNeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent Procedures
    ----------------------------------------------------------------------------
    a_1: VitalINV (
            q            => CLRint,
            a            => CLRNeg_ipd
         );

    ----------------------------------------------------------------------------
    -- Main Behavior Process
    ----------------------------------------------------------------------------
    VitalYOut : PROCESS (CLK_ipd, OENeg_ipd)

        -- Functionality Results Variables
        VARIABLE Y_zd           : std_ulogic;
     
        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData   : VitalGlitchDataType;
 
    BEGIN
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Y_zd := VitalBUFIF0 (data => CLK_ipd, enable => OENeg_ipd);
 
        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       =>  Y,
            OutSignalName   =>  "Y",
            OutTemp         =>  Y_zd,
            GlitchData      => Y_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => CLK_ipd'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_CLK_Y),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OENeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_OENeg_Y,
                      PathCondition     => TRUE))
        );

    END PROCESS;
 
    VitalQOut : PROCESS (Tint, OENeg_ipd)
 
        -- Functionality Results Variables
        VARIABLE Q_zd           : std_ulogic;
        
        -- Output Glitch Detection Variables
        VARIABLE Q_GlitchData   : VitalGlitchDataType;
 
    BEGIN
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Q_zd := VitalBUFIF0 (data => Tint, enable => OENeg_ipd);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01Z (
            OutSignal       =>  Q,
            OutSignalName   =>  "Q",
            OutTemp         =>  Q_zd,
            GlitchData      => Q_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => Tint'LAST_EVENT,
                      PathDelay         => VitalExtendToFillDelay(tpd_CLK_Y),
                      PathCondition     => TRUE),
                1 => (InputChangeTime   => OENeg_ipd'LAST_EVENT,
                      PathDelay         => tpd_OENeg_Y,
                      PathCondition     => TRUE))
        );

    END PROCESS;

    VitalBehavior : PROCESS (CLK_ipd, CLRint)

        -- Timing Check Variables
        VARIABLE Tviol_CLR_CLK  : X01 := '0';
        VARIABLE TD_CLR_CLK     : VitalTimingDataType;

        VARIABLE Pviol_CLK      : X01 := '0';
        VARIABLE PD_CLK         : VitalPeriodDataType := VitalPeriodDataInit;
 
        VARIABLE Pviol_CLR      : X01 := '0';
        VARIABLE PD_CLR         : VitalPeriodDataType := VitalPeriodDataInit;
 
        VARIABLE Violation      : X01 := '0';
 
        -- Functionality Results Variables
        VARIABLE T_zd           : std_ulogic;
        VARIABLE PrevData       : std_logic_vector(0 to 2);

        -- Output Glitch Detection Variables
        VARIABLE T_GlitchData   : VitalGlitchDataType;
 
    BEGIN
        ------------------------------------------------------------------------
        -- Timing Check Section
        ------------------------------------------------------------------------
        IF (TimingChecksOn) THEN
 
            VitalSetupHoldCheck (
                TestSignal      => CLRint,
                TestSignalName  => "CLRint",
                RefSignal       => CLK_ipd,
                RefSignalName   => "CLK_ipd",
                SetupHigh       => tsetup_CLRNeg_CLK,
                SetupLow        => tsetup_CLRNeg_CLK,
                CheckEnabled    => TRUE,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & "/cdc339",
                TimingData      => TD_CLR_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CLR_CLK
            );

            VitalPeriodPulseCheck (
                TestSignal      => CLK_ipd,
                TestSignalName  => "CLK_ipd",
                Period          => tperiod_CLK_posedge,
                PulseWidthHigh  => tpw_CLK_posedge,
                PulseWidthLow   => tpw_CLK_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & "/cdc339",
                PeriodData      => PD_CLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_CLK
            );

            VitalPeriodPulseCheck (
                TestSignal      => CLRint,
                TestSignalName  => "CLRint",
                PulseWidthLow   => tpw_CLRNeg_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & "/cdc339",
                PeriodData      => PD_CLR,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_CLR
            );

        END IF;
 
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Violation := Tviol_CLR_CLK OR Pviol_CLK OR Pviol_CLR;

        VitalStateTable (             
            StateTable      => TFFR_tab,
            DataIn          => (Violation, CLK_ipd, CLRint),
            Result          => T_zd,
            PreviousDataIn  => PrevData
        );

        ------------------------------------------------------------------------
        -- (Dummy) Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay (
            OutSignal       => Tint,
            OutSignalName   => "Tint",
            OutTemp         => T_zd,
            GlitchData      => T_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => CLK_ipd'LAST_EVENT,
                      PathDelay         => VitalZeroDelay,
                      PathCondition     => FALSE))
        );

    END PROCESS;

END vhdl_behavioral;