hghm.fdo

full ader circuit sdlj mlad f jsadfl kl sdf fjklasd as jsdjfkljkla sdfi jsakldjfk kjawkl jklasdjf

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Mon Sep 08 10:22:15 AM India Standard Time 2008
##
vlib work
vlog  +acc  "fa.v"
vcom -explicit  -93 "hghm.vhw"
vlog  +acc  "C:/Xilinx92i/verilog/src/glbl.v"
vsim -t 1ps   -L cpld_ver -L uni9000_ver -lib work hghm glbl
view wave
add wave *
add wave /glbl/PRLD
do {hghm.udo}
view structure
view signals
run 1000ns