_primary.vhd

来自「full ader circuit sdlj mlad f jsadfl kl」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity fa is
    port(
        a               : in     vl_logic;
        b               : in     vl_logic;
        c               : in     vl_logic;
        sum             : out    vl_logic;
        carry           : out    vl_logic
    );
end fa;