hghm.tfw

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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2007 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 9.2i
//  \   \         Application : ISE
//  /   /         Filename : hghm.tfw
// /___/   /\     Timestamp : Mon Sep 08 10:20:27 2008
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: 
//Design Name: hghm
//Device: Xilinx
//
`timescale 1ns/1ps

module hghm;
    reg a = 1'b0;
    reg b = 1'b0;
    reg c = 1'b0;
    wire sum;
    wire carry;

    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 100;

    initial    // Clock process for a
    begin
        #OFFSET;
        forever
        begin
            a = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) a = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end

    fa UUT (
        .a(a),
        .b(b),
        .c(c),
        .sum(sum),
        .carry(carry));

    initial begin
        // -------------  Current Time:  185ns
        #185;
        b = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  385ns
        #200;
        b = 1'b0;
        c = 1'b1;
        // -------------------------------------
        // -------------  Current Time:  585ns
        #200;
        c = 1'b0;
        // -------------------------------------
        // -------------  Current Time:  785ns
        #200;
        b = 1'b1;
        // -------------------------------------
    end

endmodule