transcript

full ader circuit sdlj mlad f jsadfl kl sdf fjklasd as jsdjfkljkla sdfi jsakldjfk kjawkl jklasdjf

# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl 
# do {hghm.fdo} 
# Model Technology ModelSim XE III vlog 6.2g Compiler 2007.02 Feb 22 2007
# -- Compiling module fa
# 
# Top level modules:
# 	fa
# Model Technology ModelSim XE III vcom 6.2g Compiler 2007.02 Feb 22 2007
# -- Loading package standard
# -- Loading package textio
# -- Loading package std_logic_1164
# -- Loading package std_logic_textio
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity hghm
# -- Compiling architecture testbench_arch of hghm
# Model Technology ModelSim XE III vlog 6.2g Compiler 2007.02 Feb 22 2007
# -- Compiling module glbl
# 
# Top level modules:
# 	glbl
# vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps hghm glbl 
# Loading C:\Modeltech_xe_starter\win32xoem/../std.standard
# Loading C:\Modeltech_xe_starter\win32xoem/../std.textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body)
# Loading C:\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body)
# Loading work.hghm(testbench_arch)
# XE version supports only a single HDL
# Error loading design
# Error: Error loading design 
#        Pausing macro execution 
# MACRO ./hghm.fdo PAUSED at line 8
vsim work.fa
# vsim work.fa 
# Loading work.fa
add wave sim:/fa/a
add wave sim:/fa/b
add wave sim:/fa/c
add wave sim:/fa/sum
add wave sim:/fa/carry
run
force -freeze sim:/fa/a 1 0, 0 {50 ps} -r 100
force -freeze sim:/fa/b 0 0, 1 {50 ps} -r 100
force -freeze sim:/fa/c 0 0, 1 {50 ps} -r 100
run
run
run
run
run
run
run
run
run