fa.stx

full ader circuit sdlj mlad f jsadfl kl sdf fjklasd as jsdjfkljkla sdfi jsakldjfk kjawkl jklasdjf

Release 9.2i - xst J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
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=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "fa.v" in library work
Module <fa> compiled
No errors in compilation
Analysis of file <"fa.prj"> succeeded.
 
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Total memory usage is 110844 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)