fa.v

来自「full ader circuit sdlj mlad f jsadfl kl」· Verilog 代码 · 共 39 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:16:41 09/08/2008 
// Design Name: 
// Module Name:    fa 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module fa(a, b, c, sum, carry);
    input a;
    input b;
    input c;
    output sum;
    output carry;
  wire s1,t1,t2,t3;
  xor 
     x1(s1,a,b),
	  x2(sum,s1,c);
  and
     a1(t1,a,b),
	  a2(t2,b,c),
	  a3(t3,c,a);
  or
    o1(carry,t1,t2,t3);

endmodule