second.fit.summary

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

Fitter Status : Successful - Tue Oct 07 18:30:04 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : second
Top-level Entity Name : second
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 171 / 2,910 ( 6 % )
Total pins : 21 / 104 ( 20 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )