prev_cmp_second.qmsg

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 07 18:27:59 2008 " "Info: Processing started: Tue Oct 07 18:27:59 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off second -c second " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off second -c second" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "second.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file second.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 second " "Info: Found entity 1: second" {  } { { "second.bdf" "" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-a " "Info: Found design unit 1: fenpin-a" {  } { { "fenpin.vhd" "" { Text "F:/FPGA_CHENGXU/second/fenpin.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "fenpin.vhd" "" { Text "F:/FPGA_CHENGXU/second/fenpin.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt_10.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt_10.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt_10-a " "Info: Found design unit 1: cnt_10-a" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt_10 " "Info: Found entity 1: cnt_10" {  } { { "cnt_10.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_10.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "xian.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file xian.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 xian-a " "Info: Found design unit 1: xian-a" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 xian " "Info: Found entity 1: xian" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt_12.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt_12.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt_12-a " "Info: Found design unit 1: cnt_12-a" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt_12 " "Info: Found entity 1: cnt_12" {  } { { "cnt_12.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_12.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt_60.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file cnt_60.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cnt_60-a " "Info: Found design unit 1: cnt_60-a" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cnt_60 " "Info: Found entity 1: cnt_60" {  } { { "cnt_60.vhd" "" { Text "F:/FPGA_CHENGXU/second/cnt_60.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fp2.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fp2.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fp2-a " "Info: Found design unit 1: fp2-a" {  } { { "fp2.vhd" "" { Text "F:/FPGA_CHENGXU/second/fp2.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fp2 " "Info: Found entity 1: fp2" {  } { { "fp2.vhd" "" { Text "F:/FPGA_CHENGXU/second/fp2.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "second " "Info: Elaborating entity \"second\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "xian xian:inst6 " "Info: Elaborating entity \"xian\" for hierarchy \"xian:inst6\"" {  } { { "second.bdf" "inst6" { Schematic "F:/FPGA_CHENGXU/second/second.bdf" { { 216 896 1056 408 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "shuju xian.vhd(23) " "Warning (10036): Verilog HDL or VHDL warning at xian.vhd(23): object \"shuju\" assigned a value but never read" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 23 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "shu1 xian.vhd(29) " "Warning (10492): VHDL Process Statement warning at xian.vhd(29): signal \"shu1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "shu2 xian.vhd(30) " "Warning (10492): VHDL Process Statement warning at xian.vhd(30): signal \"shu2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "shu3 xian.vhd(31) " "Warning (10492): VHDL Process Statement warning at xian.vhd(31): signal \"shu3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "shu4 xian.vhd(32) " "Warning (10492): VHDL Process Statement warning at xian.vhd(32): signal \"shu4\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "shu5 xian.vhd(33) " "Warning (10492): VHDL Process Statement warning at xian.vhd(33): signal \"shu5\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "shu6 xian.vhd(34) " "Warning (10492): VHDL Process Statement warning at xian.vhd(34): signal \"shu6\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "xian.vhd" "" { Text "F:/FPGA_CHENGXU/second/xian.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}