xian.vhd

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

library ieee;
use ieee.std_logic_1164.all;
entity xian is
port(
  clk: in std_logic;
 shu1: in std_logic_vector(3 downto 0);
 shu2: in std_logic_vector(3 downto 0);
 shu3: in std_logic_vector(3 downto 0);
 shu4: in std_logic_vector(3 downto 0);
 shu5: in std_logic_vector(3 downto 0);
 shu6: in std_logic_vector(3 downto 0);
 shu7: in std_logic_vector(3 downto 0);
 shu8: in std_logic_vector(3 downto 0);
 data,chose: out std_logic_vector(7 downto 0)

);

end entity xian;
architecture a of xian is
SIGNAL data1: std_logic_vector(7 downto 0);    
begin	
process(clk)
    variable shuju: std_logic_vector(7 downto 0);

	variable d1: integer range 0 to 7;
	variable cc: std_logic_vector(3 downto 0);
    begin
        case d1 is
			when 0 => cc:=shu1;
			when 1 => cc:=shu2;
			when 2 => cc:=shu3;
			when 3 => cc:=shu4;
			when 4 => cc:=shu5;
			when 5 => cc:=shu6;
			when 6 => cc:=shu7;
			when 7 => cc:=shu8;
        end case;
        case cc is
			when "0000" => data1<="11111100";
			when "0001" => data1<="01100000";
			when "0010" => data1<="11011010";
			when "0011" => data1<="11110010";
			when "0100" => data1<="01100110";
			when "0101" => data1<="10110110";
			when "0110" => data1<="10111110";
			when "0111" => data1<="11100000";
			when "1000" => data1<="11111110";
			when "1001" => data1<="11110110";
			--when 10 => data<="00000010";
			when others => shuju:="00000000";

        end case; 
        case d1 is
			when 0 => chose<="10000000";
			when 1 => chose<="01000000";
			when 2 => chose<="00100000";
			when 3 => chose<="00010000";
			when 4 => chose<="00001000";
			when 5 => chose<="00000100";
			when 6 => chose<="00000010";
			when 7 => chose<="00000001";
         end case;
        case d1 is
			when 0 => data<=data1;
			when 1 => data<=data1 or "00000001";
			when 2 => data<=data1;
			when 3 => data<=data1 or "00000001";
			when 4 => data<=data1;
			when 5 => data<=data1 or "00000001";
			when 6 => data<=data1;
			when 7 => data<=data1;
         end case;
     
		if(clk 'event and clk='1') then
		    if(d1=7) then
				d1:=0;
		    else
			    d1:=d1+1;
			end if;	
		end if;	
		
	end process;


end architecture a;