second.map.rpt

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

;     -- synchronous clear/load mode          ; 20    ;
;     -- asynchronous clear/load mode         ; 37    ;
;                                             ;       ;
; Total registers                             ; 76    ;
; Total logic cells in carry chains           ; 67    ;
; I/O pins                                    ; 21    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 37    ;
; Total fan-out                               ; 626   ;
; Average fan-out                             ; 3.00  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name  ; Library Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+--------------+
; |second                    ; 188 (0)     ; 76           ; 0           ; 21   ; 0            ; 112 (0)      ; 33 (0)            ; 43 (0)           ; 67 (0)          ; 0 (0)      ; |second              ; work         ;
;    |cnt_10:inst1|          ; 6 (6)       ; 5            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; 4 (4)           ; 0 (0)      ; |second|cnt_10:inst1 ; work         ;
;    |cnt_10:inst2|          ; 6 (6)       ; 5            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 5 (5)            ; 4 (4)           ; 0 (0)      ; |second|cnt_10:inst2 ; work         ;
;    |cnt_12:inst5|          ; 16 (16)     ; 8            ; 0           ; 0    ; 0            ; 8 (8)        ; 3 (3)             ; 5 (5)            ; 8 (8)           ; 0 (0)      ; |second|cnt_12:inst5 ; work         ;
;    |cnt_60:inst3|          ; 15 (15)     ; 9            ; 0           ; 0    ; 0            ; 6 (6)        ; 2 (2)             ; 7 (7)            ; 8 (8)           ; 0 (0)      ; |second|cnt_60:inst3 ; work         ;
;    |cnt_60:inst4|          ; 15 (15)     ; 9            ; 0           ; 0    ; 0            ; 6 (6)        ; 2 (2)             ; 7 (7)            ; 8 (8)           ; 0 (0)      ; |second|cnt_60:inst4 ; work         ;
;    |fenpin:inst|           ; 45 (45)     ; 20           ; 0           ; 0    ; 0            ; 25 (25)      ; 14 (14)           ; 6 (6)            ; 19 (19)         ; 0 (0)      ; |second|fenpin:inst  ; work         ;
;    |fp2:inst12|            ; 38 (38)     ; 17           ; 0           ; 0    ; 0            ; 21 (21)      ; 12 (12)           ; 5 (5)            ; 16 (16)         ; 0 (0)      ; |second|fp2:inst12   ; work         ;
;    |xian:inst6|            ; 47 (47)     ; 3            ; 0           ; 0    ; 0            ; 44 (44)      ; 0 (0)             ; 3 (3)            ; 0 (0)           ; 0 (0)      ; |second|xian:inst6   ; work         ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+----------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; xian:inst6|data1[7]                                ; xian:inst6|Mux22    ; yes                    ;
; xian:inst6|data1[6]                                ; xian:inst6|Mux22    ; yes                    ;
; xian:inst6|data1[5]                                ; xian:inst6|Mux22    ; yes                    ;
; xian:inst6|data1[4]                                ; xian:inst6|Mux22    ; yes                    ;
; xian:inst6|data1[3]                                ; xian:inst6|Mux22    ; yes                    ;
; xian:inst6|data1[2]                                ; xian:inst6|Mux22    ; yes                    ;
; xian:inst6|data1[1]                                ; xian:inst6|Mux22    ; yes                    ;
; Number of user-specified and inferred latches = 7  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 76    ;
; Number of registers using Synchronous Clear  ; 20    ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 37    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 19    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |second|cnt_12:inst5|QL[2] ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |second|cnt_60:inst4|QL[3] ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |second|cnt_60:inst3|QL[1] ;
; 8:1                ; 4 bits    ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; No         ; |second|xian:inst6|Mux3    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Oct 07 18:29:56 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off second -c second
Info: Found 1 design units, including 1 entities, in source file second.bdf
    Info: Found entity 1: second
Info: Found 2 design units, including 1 entities, in source file fenpin.vhd
    Info: Found design unit 1: fenpin-a
    Info: Found entity 1: fenpin
Info: Found 2 design units, including 1 entities, in source file cnt_10.vhd
    Info: Found design unit 1: cnt_10-a
    Info: Found entity 1: cnt_10
Info: Found 2 design units, including 1 entities, in source file xian.vhd
    Info: Found design unit 1: xian-a
    Info: Found entity 1: xian
Info: Found 2 design units, including 1 entities, in source file cnt_12.vhd
    Info: Found design unit 1: cnt_12-a
    Info: Found entity 1: cnt_12
Info: Found 2 design units, including 1 entities, in source file cnt_60.vhd
    Info: Found design unit 1: cnt_60-a
    Info: Found entity 1: cnt_60
Info: Found 2 design units, including 1 entities, in source file fp2.vhd
    Info: Found design unit 1: fp2-a
    Info: Found entity 1: fp2
Info: Elaborating entity "second" for the top level hierarchy
Info: Elaborating entity "xian" for hierarchy "xian:inst6"
Warning (10036): Verilog HDL or VHDL warning at xian.vhd(23): object "shuju" assigned a value but never read
Warning (10492): VHDL Process Statement warning at xian.vhd(29): signal "shu1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(30): signal "shu2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(31): signal "shu3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(32): signal "shu4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(33): signal "shu5" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(34): signal "shu6" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(35): signal "shu7" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(36): signal "shu8" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(64): signal "data1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(65): signal "data1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(66): signal "data1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(67): signal "data1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(68): signal "data1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(69): signal "data1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(70): signal "data1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at xian.vhd(71): signal "data1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at xian.vhd(22): inferring latch(es) for signal or variable "data1", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "data1[0]" at xian.vhd(22)
Info (10041): Inferred latch for "data1[1]" at xian.vhd(22)
Info (10041): Inferred latch for "data1[2]" at xian.vhd(22)
Info (10041): Inferred latch for "data1[3]" at xian.vhd(22)
Info (10041): Inferred latch for "data1[4]" at xian.vhd(22)
Info (10041): Inferred latch for "data1[5]" at xian.vhd(22)
Info (10041): Inferred latch for "data1[6]" at xian.vhd(22)
Info (10041): Inferred latch for "data1[7]" at xian.vhd(22)
Info: Elaborating entity "fp2" for hierarchy "fp2:inst12"
Info: Elaborating entity "cnt_12" for hierarchy "cnt_12:inst5"
Info: Elaborating entity "cnt_60" for hierarchy "cnt_60:inst4"
Info: Elaborating entity "cnt_10" for hierarchy "cnt_10:inst2"
Info: Elaborating entity "fenpin" for hierarchy "fenpin:inst"
Warning (10492): VHDL Process Statement warning at fenpin.vhd(19): signal "start" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning: Replaced VCC or GND feeding tri-state bus ddd~0 with an always-enabled tri-state buffer
Warning: Latch xian:inst6|data1[7] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6|d1[0]
Warning: Latch xian:inst6|data1[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6|d1[0]
Warning: Latch xian:inst6|data1[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6|d1[0]
Warning: Latch xian:inst6|data1[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6|d1[0]
Warning: Latch xian:inst6|data1[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6|d1[0]
Warning: Latch xian:inst6|data1[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6|d1[0]
Warning: Latch xian:inst6|data1[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal xian:inst6|d1[0]
Info: Implemented 209 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 16 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 188 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 34 warnings
    Info: Allocated 161 megabytes of memory during processing
    Info: Processing ended: Tue Oct 07 18:30:00 2008
    Info: Elapsed time: 00:00:04