second.map.summary

基于FPGA的秒表设计基于FPGA的秒表设计基于FPGA的秒表设计

Analysis & Synthesis Status : Successful - Tue Oct 07 18:30:00 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : second
Top-level Entity Name : second
Family : Cyclone
Total logic elements : 188
Total pins : 21
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : N/A until Partition Merge
Total PLLs : 0
Total DLLs : N/A until Partition Merge