rca-8bit.v

来自「IP core of adder,8-bit width, three desi」· Verilog 代码 · 共 102 行

`timescale 1ns/10ps
//===============================================================================
//           TOP Level --->    8-bit RCA Source Code
//                                     ---BAO Chaowei    Mar 3rd,2009
//===============================================================================
module  RCA_8bit(COUT,
                 SUM,
                 A,
                 B,
                 CIN
                 );
                 
  output         COUT;
  output  [7:0]  SUM;
  input   [7:0]  A;
  input   [7:0]  B;
  input          CIN;
  
  wire   cout0,cout1,cout2,cout3,cout4,cout5,cout6,cout7;
  
  RCA_CELL RCA_BIT0(.co     (cout0),
                    .s      (SUM[0]),
                    .a      (A[0]),
                    .b      (B[0]),
                    .ci     (CIN)
                    );
  
  RCA_CELL RCA_BIT1(.co     (cout1),
                    .s      (SUM[1]),
                    .a      (A[1]),
                    .b      (B[1]),
                    .ci     (cout0)
                    );
  
  RCA_CELL RCA_BIT2(.co     (cout2),
                    .s      (SUM[2]),
                    .a      (A[2]),
                    .b      (B[2]),
                    .ci     (cout1)
                    );
  
  RCA_CELL RCA_BIT3(.co     (cout3),
                    .s      (SUM[3]),
                    .a      (A[3]),
                    .b      (B[3]),
                    .ci     (cout2)
                    );
  
  RCA_CELL RCA_BIT4(.co     (cout4),
                    .s      (SUM[4]),
                    .a      (A[4]),
                    .b      (B[4]),
                    .ci     (cout3)
                    );

  RCA_CELL RCA_BIT5(.co     (cout5),
                    .s      (SUM[5]),
                    .a      (A[5]),
                    .b      (B[5]),
                    .ci     (cout4)
                    );

  RCA_CELL RCA_BIT6(.co     (cout6),
                    .s      (SUM[6]),
                    .a      (A[6]),
                    .b      (B[6]),
                    .ci     (cout5)
                    );

  RCA_CELL RCA_BIT7(.co     (cout7),
                    .s      (SUM[7]),
                    .a      (A[7]),
                    .b      (B[7]),
                    .ci     (cout6)
                    );

  assign   COUT  = cout7;


endmodule




//=======================1-bit cell for RCA(Ripple Carry Adder)=======================
module  RCA_CELL(co,
                 s,
                 a,
                 b,
                 ci
                 );
                 
  output    co;
  output    s;
  input     a;
  input     b;
  input     ci;
  
  assign   co = (a&&b) || (a&&ci) || (b&&ci);
  assign   s  = a^b^ci;        
    
endmodule