123.txt

sram读模块基于FPGA的实现 verilog源代码

 module refresh( clk, 
                refresh_active_in,
			 refresh_reset,
			 refresh_ras_out, 
			 refresh_cas_out, 
			 refresh_we_out , 
			 refresh_end_out
			);

/****************************************************/

	    input	 clk;		  	//时钟输入
	    input  refresh_active_in;		//刷新开始
	    input  refresh_reset;             //模块复位
	    output refresh_ras_out;
	    output refresh_cas_out;
	    output refresh_we_out;		     //工作模式组合
	    output refresh_end_out;		//刷新"结束"标志

	    wire   clk;
	    wire   refresh_active_in;
	    wire   refresh_reset;
	    wire   refresh_ras_out;
	    wire 	 refresh_cas_out;
	    wire 	 refresh_we_out;
	    wire	 refresh_end_out;
/******************************************************/

	    reg[3:0]  cnt;
	    reg[3:0]  state;
	    reg[2:0]  command;
	    reg  end_out;

 /****************************************************/

	    parameter IDLE=4'b0001,		  //空转状态
	              REFRESH=4'b0010,	  //刷新状态
	              NOP=4'b0100,		  //空操作状态
			    COUNT=4'b1000;		  //时钟计数状态

/*********************状态机*******************************/

	   always@(posedge clk or posedge refresh_reset)
	     begin
		  if(refresh_reset)state<=IDLE; 			 
		  else  
		    begin
               case(state)
			  IDLE:  
			         begin				   //空转状态
			           if(refresh_active_in)state<=REFRESH;  // 检测到do_refresh，转到刷新状态
			          end
			  REFRESH: state<=NOP;	   //转到空操作指令
			  NOP:     state<=COUNT;	   //转到计数状态     
			  COUNT: 
			         begin
			         	if(cnt==8)	state<=IDLE;  	    //计数到8个时钟周期，SDRAM刷新结束
	                    else state<=COUNT;	//循环计数
				    end
				    
		     endcase     
		   end
		 end



/**************************************************************/	  

	    always@(posedge clk or posedge refresh_reset)
	      begin
             if(refresh_reset)command<=3'b000;
		    else
		      begin
			   case(state)
			      REFRESH: command<=3'b001;                     
				 NOP:  command<=3'b000;

			   endcase
			 end
		 end

/***************************************************************/

	    always@(posedge clk or posedge refresh_reset)
	     begin
		  if(refresh_reset)cnt<=0;
		  else begin
		       case(state)
		    	     COUNT: begin
			         if(cnt==8)	    //计数到8个时钟周期，刷新结束
                           cnt<=0;
					else cnt<=cnt+1;
				   end
		       endcase
		      end
		 end

 /***********************************************************/

	   always@(posedge clk or posedge refresh_reset)
	     begin
	      if(refresh_reset)end_out<=0;
		 else
		      begin
			   case(state)
			      COUNT:if(cnt==8)end_out<=1;
			   endcase
			  end
		end

 /**********************************************************/

    assign refresh_ras_out=command[2];
    assign refresh_cas_out=command[1];
    assign refresh_we_out=command[0];
    assign refresh_end_out=end_out;

endmodule