test.v

用Verilog实现的序列检测器

`timescale 1ns/1ns
module test();
  reg din,clk,rst;
  wire q_out;
  
  //instance
  check uut(q_out,din,clk,rst);
  
  //set up display 
  initial
    begin
      $shm_open ("shm1.db");
      $shm_probe ("AS");
    end
    
  //define clock
  initial
  clk = 0;

  always
  begin
    #10 clk = 1; //time 10
    #10 clk = 0; //time 10 later than the last
  end  
  
  //apply simulus
  initial begin
    rst=0;
  @(posedge clk)
    din=1;
  @(negedge clk)
    rst=1; 
  @(posedge clk)
    din=0;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=0;
  @(posedge clk)
    din=1;  
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=0;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=0;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=0;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=0;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=1;
  @(posedge clk)
    din=0; 
                           
  #40 $finish;
  end
  
endmodule