check.v

来自「用Verilog实现的序列检测器」· Verilog 代码 · 共 88 行

`timescale 1ns/1ns
module check(q_out,din,clk,rst);
  output q_out;
  input din,clk,rst;
  
  reg q_out;
  
  parameter[2:0]
    S0=3'b000,
    S1=3'b001,
    S2=3'b010,
    S3=3'b011,
    S4=3'b100;
    
  reg[2:0] state,next_state;
  
  always@(posedge clk or negedge rst)
    begin
      if(!rst)
        state=S0;
      else
        state=next_state;
    end
    
  always@(state or din)
    begin
      case(state)
        S0:begin
             if(!din)
               next_state=S0;
             else
               next_state=S1;
           end        
        S1:begin
             if(!din)
               next_state=S2;
             else
               next_state=S1;
           end  
        S2:begin
             if(!din)
               next_state=S0;
             else
               next_state=S3;
           end  
        S3:begin
             if(!din)
               next_state=S2;
             else
               next_state=S4;
           end  
        S4:begin
             if(!din)
               next_state=S2;
             else
               next_state=S1;
           end
        default:
               next_state=3'bz;
      endcase              
    end
    
  always@(state or din)
    begin
      if(state==S4 && din==1'b0)
        q_out=1'b1;
      else
        q_out=1'b0;
    end
    
endmodule