verilog.log

用Verilog实现的序列检测器

Host command: /eda/cadence06/IUS5.7_ins/tools/verilog/bin/verilog.exe
Command arguments:
    test.v
    check.v

Tool:	VERILOG-XL	05.70.001-p log file created Nov 25, 2008  13:19:27
Tool:	VERILOG-XL	05.70.001-p   Nov 25, 2008  13:19:27

Copyright (c) 1995-2004 Cadence Design Systems, Inc.  All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.

Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc.  Reproduced with Permission.

THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC.  USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.

                Cadence Design Systems, Inc.
                555 River Oaks Parkway
                San Jose, California  95134

For technical assistance please contact the Cadence Response Center at
1-877-CDS-4911 or send email to [e-mail]

For more information on Cadence's Verilog-XL product line send email to
[e-mail]

Compiling source file "test.v"
Compiling source file "check.v"
Highest level modules:
test

L72 "test.v": $finish at simulation time 430
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of Tool:	VERILOG-XL	05.70.001-p   Nov 25, 2008  13:19:27