verilog.log

来自「用Verilog实现的序列检测器」· LOG 代码 · 共 45 行

Host command: /eda/cadence06/IUS5.7_ins/tools/verilog/bin/verilog.exe
Command arguments:
    test.v
    check.v

Tool:	VERILOG-XL	05.70.001-p log file created Nov 25, 2008  13:19:27
Tool:	VERILOG-XL	05.70.001-p   Nov 25, 2008  13:19:27

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Compiling source file "test.v"
Compiling source file "check.v"
Highest level modules:
test

L72 "test.v": $finish at simulation time 430
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.0 secs to link + 0.1 secs in simulation
End of Tool:	VERILOG-XL	05.70.001-p   Nov 25, 2008  13:19:27