reg10.log

VHDL实例

====================================================
= vvToForm v0.1 VHDL to Verilog RTL transformer
= Release: Brier EDA Studio 
= *** All Rights Reserved By Brier Van ****
====================================================
/*
library ieee;
*/
/*
use ieee.std_logic_1164.all;
*/
/*
use ieee.std_logic_unsigned.all;
*/
//------------------------------------------------------------------------
//  Crypto Chip
//  Copyright (C) 1999, Projektgruppe WS98/99
//  University of Stuttgart / Department of Computer Science / IFI-RA
//------------------------------------------------------------------------
// Designers : Arno Wacker
// Group     : RSA
//------------------------------------------------------------------
// Design Unit Name : reg10 
// Purpose :  Part of the RSA-module-core for the cryptochip "pg99"
// 
// File Name :  reg10.vhd
//------------------------------------------------------------------
// Simulator : SYNOPSYS VHDL System Simulator (VSS) Version 3.2.a
//------------------------------------------------------------------
// Date            | Changes
// 11.01.99        | 11.01.99
//                 |
//---------------------------------------------------------------------
//------------------------------------------------------------------------
//  Was implementiert wird
//  Ein einfaches 10-Bit Register. Ein Teil des B768 Zaehlers
//------------------------------------------------------------------------

module reg10(
clk,
reset,
d_in,
d_out
);

input clk, reset;
input[9:0]d_in;
output[9:0]d_out;


wire   clk;
wire   reset;
wire  [9:0]d_in;
reg  [9:0]d_out;



  // purpose: 10-Bit Register mit synchronem Takteingang
  // type:    memorizing
  // inputs:  clk, reset, d_in
  // outputs: d_out
  always @(posedge clk)
  begin
    // proces
          if(reset == 1'b 0)
      begin
        d_out <= d_in;
      end
      else
      begin
        d_out <= {10{1'b 0}};
      end
  end


endmodule
Translate D:\DesignSoftware\vhdl to verilog\example\reg10.vhd  to  D:\DesignSoftware\vhdl to verilog\example\reg10.v Finished!