ex1.rpt

用HDPLD实现的高速并行乘法器

LC11 -> - - * - - - - - - - - - - | * - - - | <-- |7483:31|~25~3
LC8  -> - - - - - - * - - - - - - | * - - - | <-- |7483:31|~52~2
LC7  -> - - - - - - * - - - - - - | * - - - | <-- |7483:31|~52~4
LC10 -> - - - - - - * - - - - - - | * - - - | <-- |7483:31|~52~5

Pin
21   -> * - - - - - - - - - - - - | * - - - | <-- AS
12   -> - * * * - * - * * * * * * | * * * * | <-- A0
17   -> - * * * * * - * * * * * * | * * * * | <-- A1
9    -> - * * * * * - * * * * * * | * * * * | <-- A2
13   -> - - * * * * - * * * * * * | * * * * | <-- A3
20   -> * - - - - - - - - - - - - | * - - - | <-- BS
14   -> - * * * * * - * * * * * * | * * * * | <-- B0
5    -> - * * * * - - * * * * * * | * * * * | <-- B1
6    -> - * * - * * - * * * * * * | * * * * | <-- B2
7    -> - - * * * * - * * * - - - | * * * * | <-- B3
LC64 -> - - * - - - - - - - - - - | * - - - | <-- |7483:31|~25~2
LC54 -> - - - - * - - - - - - - - | * - - - | <-- |7483:31|~30~2
LC55 -> - - - - * - - - - - - - - | * - - - | <-- |7483:31|~30~3
LC32 -> - - - - - - * - - - - - - | * - - - | <-- |7483:31|~52~3
LC44 -> - - - - - - * - - - - - - | * - - - | <-- |7483:31|~52~6
LC25 -> - - - - - - - - - - - - * | * - - - | <-- |7483:32|~29~2
LC24 -> - - - - - - - - - - - - * | * - - - | <-- |7483:32|~29~3
LC22 -> - * - - - - - - - - - - - | * - - - | <-- |7483:32|S1~1
LC17 -> - - - - - * - * * * - - - | * - * - | <-- |7483:32|C4
LC33 -> - - * * - * - * * * * * - | * - * * | <-- |7483:33|C4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                        e:\ex1.rpt
ex1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                                       Logic cells placed in LAB 'B'
        +----------------------------- LC21 P3
        | +--------------------------- LC20 P4
        | | +------------------------- LC26 |7483:31|~20~2
        | | | +----------------------- LC27 |7483:31|~20~3
        | | | | +--------------------- LC29 |7483:31|~20~4
        | | | | | +------------------- LC23 |7483:31|~22~1
        | | | | | | +----------------- LC31 |7483:31|S1~1
        | | | | | | | +--------------- LC32 |7483:31|~52~3
        | | | | | | | | +------------- LC19 |7483:31|~54~1
        | | | | | | | | | +----------- LC30 |7483:31|~54~3
        | | | | | | | | | | +--------- LC28 |7483:32|~2~1
        | | | | | | | | | | | +------- LC25 |7483:32|~29~2
        | | | | | | | | | | | | +----- LC24 |7483:32|~29~3
        | | | | | | | | | | | | | +--- LC22 |7483:32|S1~1
        | | | | | | | | | | | | | | +- LC17 |7483:32|C4
        | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'B':
LC31 -> * - - - - - - - - - - - - - - | - * - - | <-- |7483:31|S1~1
LC30 -> - * - - - - - - * - - - - - - | - * - - | <-- |7483:31|~54~3

Pin
12   -> * * * * - - * * * * - * - * - | * * * * | <-- A0
17   -> - * * * * - * * * * - * * * - | * * * * | <-- A1
9    -> - - * * * - * * * * - * * * - | * * * * | <-- A2
13   -> - * * * * * - * * * - * * - - | * * * * | <-- A3
14   -> - * * * * - * * * * - * * * - | * * * * | <-- B0
5    -> - * * * * - * * * * - * * * - | * * * * | <-- B1
6    -> * * * * * - * * * * - * * * - | * * * * | <-- B2
7    -> * * - - - * * * * * - - - - - | * * * * | <-- B3
LC49 -> - * - - - - - - - - - - - - - | - * * * | <-- |7483:31|~20~1
LC61 -> - * - - - - - - - - - - - - - | - * - - | <-- |7483:31|S2~1
LC42 -> - * - - - - - - - - - - - - - | - * - - | <-- |7483:31|S2~2
LC60 -> - - - - - - - - * - - - - - - | - * - - | <-- |7483:31|~54~2
LC2  -> - - - - - * - - - - * - - - * | - * - - | <-- |7483:32|~2~2
LC15 -> - - - - - * - - - - * - - - * | - * - - | <-- |7483:32|~2~3
LC1  -> * * - - - - - - * - - - - - - | - * * * | <-- |7483:32|~29~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                        e:\ex1.rpt
ex1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'C':

                                         Logic cells placed in LAB 'C'
        +------------------------------- LC46 P0
        | +----------------------------- LC41 P1
        | | +--------------------------- LC37 P6
        | | | +------------------------- LC40 P7
        | | | | +----------------------- LC35 |7483:31|~2~2
        | | | | | +--------------------- LC36 |7483:31|~2~3
        | | | | | | +------------------- LC47 |7483:31|~2~4
        | | | | | | | +----------------- LC34 |7483:31|~2~5
        | | | | | | | | +--------------- LC38 |7483:31|~2~6
        | | | | | | | | | +------------- LC43 |7483:31|~2~7
        | | | | | | | | | | +----------- LC45 |7483:31|~21~6
        | | | | | | | | | | | +--------- LC39 |7483:31|~34~2
        | | | | | | | | | | | | +------- LC48 |7483:31|~34~3
        | | | | | | | | | | | | | +----- LC42 |7483:31|S2~2
        | | | | | | | | | | | | | | +--- LC44 |7483:31|~52~6
        | | | | | | | | | | | | | | | +- LC33 |7483:33|C4
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'C'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'C':
LC35 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7483:31|~2~2
LC36 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7483:31|~2~3
LC47 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7483:31|~2~4
LC34 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7483:31|~2~5
LC38 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7483:31|~2~6
LC43 -> - - - * - - - - - - - - - - - - | - - * - | <-- |7483:31|~2~7
LC33 -> - - - * * * * * * * * * * - - - | * - * * | <-- |7483:33|C4

Pin
12   -> * * * * * * * * * * * * * * - * | * * * * | <-- A0
17   -> - * - - * * * * * * * * * * * * | * * * * | <-- A1
9    -> - - - * * * * * * * * * * * * * | * * * * | <-- A2
13   -> - - * * * * * * * * * * * * * * | * * * * | <-- A3
14   -> * * * - * * * * * * * * * * * * | * * * * | <-- B0
5    -> - * * - * * * * * * * * * * * * | * * * * | <-- B1
6    -> - - * * * * * * * * * * * * * - | * * * * | <-- B2
7    -> - - * * * * * * * * - * * * * - | * * * * | <-- B3
LC49 -> - - * - - - - - - - - - - - - - | - * * * | <-- |7483:31|~20~1
LC50 -> - - * - - - - - - - - - - - - - | - - * * | <-- |7483:31|~21~1
LC23 -> - - * * * * * * * * - - - - - - | - - * - | <-- |7483:31|~22~1
LC4  -> - - * - - - - - - - - - - - - - | - - * * | <-- |7483:31|~25~1
LC56 -> - - - * * * * * * * - - - - - - | - - * - | <-- |7483:31|~34~1
LC59 -> - - * - - - - - - - - - - - - - | - - * - | <-- |7483:31|S4~1
LC58 -> - - * - - - - - - - - - - - - - | - - * - | <-- |7483:31|S4~2
LC57 -> - - * - - - - - - - - - - - - - | - - * - | <-- |7483:31|S4~3
LC9  -> - - - * * * * * * * - - - - - - | - - * - | <-- |7483:31|~52~1
LC28 -> - - - - - - - - - * - - - - - - | - - * - | <-- |7483:32|~2~1
LC1  -> - - * - - - - - - * - - - - - - | - * * * | <-- |7483:32|~29~1
LC17 -> - - * * - - - - - * - * * - - - | * - * - | <-- |7483:32|C4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                        e:\ex1.rpt
ex1

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'D':

                                         Logic cells placed in LAB 'D'
        +------------------------------- LC51 P5
        | +----------------------------- LC49 |7483:31|~20~1
        | | +--------------------------- LC50 |7483:31|~21~1
        | | | +------------------------- LC52 |7483:31|~21~2
        | | | | +----------------------- LC62 |7483:31|~21~3
        | | | | | +--------------------- LC63 |7483:31|~21~4
        | | | | | | +------------------- LC53 |7483:31|~21~5
        | | | | | | | +----------------- LC64 |7483:31|~25~2
        | | | | | | | | +--------------- LC54 |7483:31|~30~2
        | | | | | | | | | +------------- LC55 |7483:31|~30~3
        | | | | | | | | | | +----------- LC56 |7483:31|~34~1
        | | | | | | | | | | | +--------- LC61 |7483:31|S2~1
        | | | | | | | | | | | | +------- LC59 |7483:31|S4~1
        | | | | | | | | | | | | | +----- LC58 |7483:31|S4~2
        | | | | | | | | | | | | | | +--- LC57 |7483:31|S4~3
        | | | | | | | | | | | | | | | +- LC60 |7483:31|~54~2
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'D'
LC      | | | | | | | | | | | | | | | | | A B C D |     Logic cells that feed LAB 'D':
LC49 -> * - - - - - - - - - - - * * * - | - * * * | <-- |7483:31|~20~1
LC50 -> * - - - - - - - - - - - * * * - | - - * * | <-- |7483:31|~21~1
LC52 -> * - * - - - - - - - * - - - - - | - - - * | <-- |7483:31|~21~2
LC62 -> * - * - - - - - - - * - - - - - | - - - * | <-- |7483:31|~21~3
LC63 -> * - * - - - - - - - - - - - - - | - - - * | <-- |7483:31|~21~4
LC53 -> * - * - - - - - - - * - - - - - | - - - * | <-- |7483:31|~21~5

Pin
12   -> - - - * * * * * * * - - * * * * | * * * * | <-- A0
17   -> * * * * * * * * * * * * * * * * | * * * * | <-- A1
9    -> * - * * * * * * * - * * * * * * | * * * * | <-- A2
13   -> * - * * * * * * * - * - * * * * | * * * * | <-- A3
14   -> - - - * * * * * * * - * * * * * | * * * * | <-- B0
5    -> - - - * * * * * * * - * * * * * | * * * * | <-- B1
6    -> * - * * * * - * * * * * * * * * | * * * * | <-- B2
7    -> * * * * * * * * * * * - * * * * | * * * * | <-- B3
LC26 -> * * - - - - - - - - - - - - - - | - - - * | <-- |7483:31|~20~2
LC27 -> * * - - - - - - - - - - - - - - | - - - * | <-- |7483:31|~20~3
LC29 -> * * - - - - - - - - - - - - - - | - - - * | <-- |7483:31|~20~4
LC45 -> * - * - - - - - - - - - - - - - | - - - * | <-- |7483:31|~21~6
LC4  -> * - - - - - - - - - - - - - - - | - - * * | <-- |7483:31|~25~1
LC12 -> * - - - - - - - - - - - - - - - | - - - * | <-- |7483:31|~30~1
LC39 -> - - - - - - - - - - * - - - - - | - - - * | <-- |7483:31|~34~2
LC48 -> - - - - - - - - - - * - - - - - | - - - * | <-- |7483:31|~34~3
LC6  -> - - - - - - - - - - * - - - - - | - - - * | <-- |7483:31|~34~4
LC19 -> * - - - - - - - - - - - - - - - | - - - * | <-- |7483:31|~54~1
LC1  -> - - - - - - - - * * - * * * * * | - * * * | <-- |7483:32|~29~1
LC33 -> * - * * * * * * - - * - - - - - | * - * * | <-- |7483:33|C4


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                        e:\ex1.rpt
ex1

** EQUATIONS **

AS       : INPUT;
A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
BS       : INPUT;
B0       : INPUT;
B1       : INPUT;
B2       : INPUT;
B3       : INPUT;

-- Node name is 'PS' 
-- Equation name is 'PS', location is LC005, type is output.
 PS      = LCELL( AS $  BS);

-- Node name is 'P0' 
-- Equation name is 'P0', location is LC046, type is output.
 P0      = LCELL( _EQ001 $  GND);
  _EQ001 =  A0 &  B0;

-- Node name is 'P1' 
-- Equation name is 'P1', location is LC041, type is output.
 P1      = LCELL( _EQ002 $  GND);
  _EQ002 = !A0 &  A1 &  B0
         #  A1 &  B0 & !B1
         #  A0 & !A1 &  B1
         #  A0 & !B0 &  B1;

-- Node name is 'P2' 
-- Equation name is 'P2', location is LC003, type is output.
 P2      = LCELL( _EQ003 $  _EQ004);
  _EQ003 = !A0 &  A1 &  A2 &  B0 &  B1 & !_LC022 &  _X001
         #  A0 &  A1 & !B0 &  B1 &  B2 & !_LC022 &  _X001
         #  A0 &  A2 &  B0 &  B2 & !_LC022 &  _X001
         #  A0 & !A2 &  B0 & !B2 & !_LC022 &  _X001;
  _X001  = EXP(!B0 & !B1 & !B2);
  _EQ004 = !_LC022 &  _X001;
  _X001  = EXP(!B0 & !B1 & !B2);

-- Node name is 'P3' 
-- Equation name is 'P3', location is LC021, type is output.
 P3      = LCELL( _EQ005 $ !_LC001);
  _EQ005 = !_LC031 &  _X002;
  _X002  = EXP( A0 & !B2 &  B3);

-- Node name is 'P4' 
-- Equation name is 'P4', location is LC020, type is output.
 P4      = LCELL( _EQ006 $  _EQ007);
  _EQ006 =  A0 &  B3 & !_LC061 &  _X003;
  _X003  = EXP(!B2 & !_LC001);
  _EQ007 = !_LC030 & !_LC042 & !_LC049 &  _X004;
  _X004  = EXP(!A0 &  A1 &  A3 & !B0 &  B1 &  B3);

-- Node name is 'P5' 
-- Equation name is 'P5', location is LC051, type is output.
 P5      = LCELL( _EQ008 $  GND);
  _EQ008 =  _LC004 & !_LC026 & !_LC027 & !_LC029 & !_LC045 & !_LC052 & 
             !_LC053 & !_LC062 & !_LC063 &  _X005 &  _X006 &  _X007
         #  _LC004 &  _LC012 & !_LC045 & !_LC052 & !_LC053 & !_LC062 & 
             !_LC063 &  _X006 &  _X007
         #  _LC004 &  _LC019 & !_LC045 & !_LC052 & !_LC053 & !_LC062 & 
             !_LC063 &  _X006 &  _X007
         # !_LC012 & !_LC019 & !_LC049 &  _LC050
         # !_LC004 & !_LC012 & !_LC019 & !_LC049;
  _X005  = EXP( A1 &  B3);
  _X006  = EXP(!A1 & !A2 & !A3 & !_LC033);
  _X007  = EXP(!B2 & !B3 & !_LC033);

-- Node name is 'P6' 
-- Equation name is 'P6', location is LC037, type is output.
 P6      = LCELL( _EQ009 $  _EQ010);
  _EQ009 =  _X008 &  _X009 &  _X010;
  _X008  = EXP(!B3 & !_LC023);
  _X009  = EXP(!A3 & !_LC023);
  _X010  = EXP(!_LC017 & !_LC023);
  _EQ010 = !_LC057 & !_LC058 & !_LC059 &  _X011 &  _X012 &  _X013;
  _X011  = EXP( A0 & !B0 & !B1 &  B3 &  _LC001 & !_LC049 & !_LC050);
  _X012  = EXP( A0 & !B2 &  B3 &  _LC001 & !_LC049 & !_LC050);
  _X013  = EXP(!_LC004 & !_LC050);

-- Node name is 'P7' 
-- Equation name is 'P7', location is LC040, type is output.
 P7      = LCELL( _EQ011 $  VCC);
  _EQ011 = !_LC034 & !_LC035 & !_LC036 & !_LC038 & !_LC043 & !_LC047 &  _X014 & 
              _X015;
  _X014  = EXP( A0 &  A3 &  B3 & !_LC009 &  _LC017 & !_LC023 & !_LC056);
  _X015  = EXP( A2 & !B2 &  B3 & !_LC009 & !_LC023 &  _LC033 & !_LC056);

-- Node name is '|7483:31|~42~1' = '|7483:31|S1~1' 
-- Equation name is '_LC031', type is buried 
-- synthesized logic cell 
_LC031   = LCELL( _EQ012 $  GND);