ex1.rpt
来自「用HDPLD实现的高速并行乘法器」· RPT 代码 · 共 1,223 行 · 第 1/4 页
RPT
1,223 行
-- Node name is '|7483:31|~34~2'
-- Equation name is '_LC039', type is buried
-- synthesized logic cell
_LC039 = LCELL( _EQ045 $ GND);
_EQ045 = A0 & !A1 & A2 & B0 & B1 & B2 & !B3 & _LC033
# A0 & !A2 & A3 & B0 & B1 & B2 & !_LC017 & _LC033
# A0 & !A2 & A3 & B0 & B1 & B2 & !B3 & _LC033
# !A0 & A1 & !A2 & B0 & B1 & !_LC017 & !_LC033
# A0 & A1 & !A2 & !B0 & B1 & !_LC017 & !_LC033;
-- Node name is '|7483:31|~34~3'
-- Equation name is '_LC048', type is buried
-- synthesized logic cell
_LC048 = LCELL( _EQ046 $ GND);
_EQ046 = A0 & A1 & !A2 & !B0 & B1 & !B3 & !_LC033
# !A0 & A1 & !A2 & B0 & B1 & !B3 & !_LC033
# !A2 & A3 & !B1 & B2 & !_LC017 & _LC033
# !A2 & A3 & !B1 & B2 & !B3 & _LC033
# !A0 & !A2 & A3 & !B0 & B2 & !_LC017 & _LC033;
-- Node name is '|7483:31|~34~4'
-- Equation name is '_LC006', type is buried
-- synthesized logic cell
_LC006 = LCELL( _EQ047 $ GND);
_EQ047 = !A0 & !A2 & A3 & !B0 & B2 & !B3 & _LC033
# !A1 & !A2 & A3 & B2 & !_LC017 & _LC033
# !A1 & !A2 & A3 & B2 & !B3 & _LC033
# !A2 & !A3 & !B2 & !_LC033
# !A2 & !B2 & !_LC017 & !_LC033;
-- Node name is '|7483:31|~52~1'
-- Equation name is '_LC009', type is buried
-- synthesized logic cell
_LC009 = LCELL( _EQ048 $ VCC);
_EQ048 = !_LC007 & !_LC008 & !_LC010 & !_LC032 & !_LC044;
-- Node name is '|7483:31|~52~2'
-- Equation name is '_LC008', type is buried
-- synthesized logic cell
_LC008 = LCELL( _EQ049 $ GND);
_EQ049 = !A1 & A2 & A3 & !B0 & B1 & B2 & !_LC017 & !_LC033
# A0 & !A1 & !A3 & B0 & B1 & B2 & _LC033
# A0 & A1 & !A2 & A3 & !B0 & B2 & !B3
# !A1 & A2 & A3 & !B0 & B1 & B2 & !B3
# A0 & !A1 & A3 & B0 & !B1 & !_LC017 & !_LC033;
-- Node name is '|7483:31|~52~3'
-- Equation name is '_LC032', type is buried
-- synthesized logic cell
_LC032 = LCELL( _EQ050 $ GND);
_EQ050 = A0 & A1 & A3 & B0 & B1 & !B3
# !A0 & A1 & B0 & B1 & B2 & !B3
# A0 & A1 & !A2 & B0 & !B2 & !B3
# A0 & !A1 & !A3 & B0 & B1 & !B3
# A0 & !A1 & A3 & B0 & !B1 & !B3;
-- Node name is '|7483:31|~52~4'
-- Equation name is '_LC007', type is buried
-- synthesized logic cell
_LC007 = LCELL( _EQ051 $ GND);
_EQ051 = A0 & A1 & !A3 & B0 & !B1 & !B3
# A1 & A2 & !A3 & !B0 & B1 & !B3
# !A1 & A2 & B0 & !B2 & !_LC017 & !_LC033
# A1 & A2 & A3 & B0 & !B3
# !A1 & A2 & B0 & !B2 & !B3;
-- Node name is '|7483:31|~52~5'
-- Equation name is '_LC010', type is buried
-- synthesized logic cell
_LC010 = LCELL( _EQ052 $ GND);
_EQ052 = !A1 & !B1 & !B2 & !_LC017 & !_LC033
# !A1 & !A3 & !B2 & !_LC033
# !A3 & !B0 & !B2 & !B3
# !A0 & !A2 & !A3 & !B3
# !A1 & !A2 & !B1 & !_LC017;
-- Node name is '|7483:31|~52~6'
-- Equation name is '_LC044', type is buried
-- synthesized logic cell
_LC044 = LCELL( _EQ053 $ GND);
_EQ053 = !A1 & !A2 & !B1 & !B3
# !A2 & !B0 & !B1 & !B3
# !A1 & !A2 & !A3
# !B1 & !B2 & !B3;
-- Node name is '|7483:31|~54~1'
-- Equation name is '_LC019', type is buried
-- synthesized logic cell
_LC019 = LCELL( _EQ054 $ _EQ055);
_EQ054 = A0 & A1 & A2 & !A3 & B0 & B1 & B3 & !_LC030 & !_LC060 &
_X004 & _X017 & _X018
# A0 & A1 & !A2 & !A3 & B1 & B2 & B3 & !_LC030 & !_LC060 &
_X004 & _X017 & _X018
# A1 & !A2 & A3 & B0 & !B1 & B2 & B3 & !_LC030 & !_LC060 &
_X004 & _X017 & _X018;
_X004 = EXP(!A0 & A1 & A3 & !B0 & B1 & B3);
_X017 = EXP( A0 & !A1 & !B0 & B3 & _LC001);
_X018 = EXP( A0 & !B2 & B3 & _LC001);
_EQ055 = !_LC030 & !_LC060 & _X004 & _X017 & _X018;
_X004 = EXP(!A0 & A1 & A3 & !B0 & B1 & B3);
_X017 = EXP( A0 & !A1 & !B0 & B3 & _LC001);
_X018 = EXP( A0 & !B2 & B3 & _LC001);
-- Node name is '|7483:31|~54~2'
-- Equation name is '_LC060', type is buried
-- synthesized logic cell
_LC060 = LCELL( _EQ056 $ GND);
_EQ056 = A0 & A1 & !B0 & B1 & B2 & B3 & !_LC001
# A1 & A3 & !B0 & B1 & B3 & !_LC001
# A0 & A2 & B0 & B2 & B3 & !_LC001
# A0 & !A2 & B0 & B3 & _LC001
# A0 & !B0 & !B1 & B3 & _LC001;
-- Node name is '|7483:31|~54~3'
-- Equation name is '_LC030', type is buried
-- synthesized logic cell
_LC030 = LCELL( _EQ057 $ GND);
_EQ057 = A1 & A2 & !A3 & B0 & B1 & !B2 & B3
# !A0 & A1 & A2 & !A3 & !B1 & B2 & B3
# !A0 & A1 & !A2 & A3 & B1 & !B2 & B3
# A1 & A2 & A3 & !B0 & B1 & B3
# A1 & A2 & !B0 & !B1 & B2 & B3;
-- Node name is '|7483:32|:83' = '|7483:32|C4'
-- Equation name is '_LC017', type is buried
_LC017 = LCELL( _EQ058 $ VCC);
_EQ058 = !_LC002 & !_LC015;
-- Node name is '|7483:32|~42~1' = '|7483:32|S1~1'
-- Equation name is '_LC022', type is buried
-- synthesized logic cell
_LC022 = LCELL( _EQ059 $ GND);
_EQ059 = !A1 & !B0 & !B2
# !A0 & !A1 & !B0
# !A0 & !A1 & !A2
# !A0 & !B0 & !B1
# !A0 & !A2 & !B1;
-- Node name is '|7483:32|~2~1'
-- Equation name is '_LC028', type is buried
-- synthesized logic cell
_LC028 = LCELL( _EQ060 $ VCC);
_EQ060 = !_LC002 & !_LC015;
-- Node name is '|7483:32|~2~2'
-- Equation name is '_LC002', type is buried
-- synthesized logic cell
_LC002 = LCELL( _EQ061 $ GND);
_EQ061 = !A0 & A1 & A3 & B0 & B1 & B2
# A0 & A1 & A3 & !B0 & B1 & B2
# A0 & A2 & B0 & B1 & B2 & _LC033
# A0 & A1 & A2 & B0 & B2 & _LC033
# A1 & A2 & B1 & B2 & _LC033;
-- Node name is '|7483:32|~2~3'
-- Equation name is '_LC015', type is buried
-- synthesized logic cell
_LC015 = LCELL( _EQ062 $ GND);
_EQ062 = A0 & A2 & A3 & B0 & !B1 & B2
# A2 & A3 & !B0 & B1 & B2
# A1 & A2 & A3 & B1 & B2
# A1 & A2 & A3 & B0 & B2
# A3 & B2 & _LC033;
-- Node name is '|7483:32|~29~1'
-- Equation name is '_LC001', type is buried
-- synthesized logic cell
_LC001 = LCELL( _EQ063 $ _EQ064);
_EQ063 = A0 & !A2 & !A3 & B0 & B1 & B2 & !_LC024 & !_LC025 & _X001 &
_X019
# A0 & A1 & !A2 & A3 & B1 & !B2 & !_LC024 & !_LC025 & _X001 &
_X019
# A2 & A3 & B0 & B1 & B2 & !_LC024 & !_LC025 & _X001 & _X019
# !A0 & A1 & A3 & B0 & B2 & !_LC024 & !_LC025 & _X001 & _X019;
_X001 = EXP(!B0 & !B1 & !B2);
_X019 = EXP(!A2 & !B0 & !B2);
_EQ064 = !_LC024 & !_LC025 & _X001 & _X019;
_X001 = EXP(!B0 & !B1 & !B2);
_X019 = EXP(!A2 & !B0 & !B2);
-- Node name is '|7483:32|~29~2'
-- Equation name is '_LC025', type is buried
-- synthesized logic cell
_LC025 = LCELL( _EQ065 $ GND);
_EQ065 = !A1 & A2 & A3 & B0 & B1
# A1 & A3 & B0 & !B1 & B2
# A1 & A2 & !B0 & B1 & B2
# A1 & A2 & !A3 & B0 & !B2
# !A0 & A1 & !A3 & B0 & !B2;
-- Node name is '|7483:32|~29~3'
-- Equation name is '_LC024', type is buried
-- synthesized logic cell
_LC024 = LCELL( _EQ066 $ GND);
_EQ066 = !A1 & !A2 & !A3
# !A1 & !A3 & !B1
# !A3 & !B1 & !B2
# !A1 & !B0 & !B1
# !A1 & !A2 & !B0;
-- Node name is '|7483:33|:83' = '|7483:33|C4'
-- Equation name is '_LC033', type is buried
_LC033 = LCELL( _EQ067 $ GND);
_EQ067 = A0 & A1 & A3 & B0 & B1
# A2 & A3 & B0 & B1;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\ex1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,031K
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