serial_uart_top.sim.rpt

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; |serial_uart_top|deal:inst2|data_led_1[6]                       ; |serial_uart_top|deal:inst2|data_led_1[6]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_1[5]                       ; |serial_uart_top|deal:inst2|data_led_1[5]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_1[4]                       ; |serial_uart_top|deal:inst2|data_led_1[4]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_1[3]                       ; |serial_uart_top|deal:inst2|data_led_1[3]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_1[2]                       ; |serial_uart_top|deal:inst2|data_led_1[2]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_1[1]                       ; |serial_uart_top|deal:inst2|data_led_1[1]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_1[0]                       ; |serial_uart_top|deal:inst2|data_led_1[0]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_2[5]                       ; |serial_uart_top|deal:inst2|data_led_2[5]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_2[4]                       ; |serial_uart_top|deal:inst2|data_led_2[4]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_2[3]                       ; |serial_uart_top|deal:inst2|data_led_2[3]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_2[2]                       ; |serial_uart_top|deal:inst2|data_led_2[2]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_2[1]                       ; |serial_uart_top|deal:inst2|data_led_2[1]                       ; regout           ;
; |serial_uart_top|deal:inst2|data_led_2[0]                       ; |serial_uart_top|deal:inst2|data_led_2[0]                       ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[4]       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[4]       ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[5]       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[5]       ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[6]       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[6]       ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[7]       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[7]       ; regout           ;
; |serial_uart_top|deal:inst2|WideOr1~17                          ; |serial_uart_top|deal:inst2|WideOr1~17                          ; combout          ;
; |serial_uart_top|deal:inst2|WideOr2~19                          ; |serial_uart_top|deal:inst2|WideOr2~19                          ; combout          ;
; |serial_uart_top|deal:inst2|WideOr3~17                          ; |serial_uart_top|deal:inst2|WideOr3~17                          ; combout          ;
; |serial_uart_top|deal:inst2|WideOr4~15                          ; |serial_uart_top|deal:inst2|WideOr4~15                          ; combout          ;
; |serial_uart_top|deal:inst2|WideOr5~19                          ; |serial_uart_top|deal:inst2|WideOr5~19                          ; combout          ;
; |serial_uart_top|deal:inst2|WideOr6~15                          ; |serial_uart_top|deal:inst2|WideOr6~15                          ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[0]       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[0]       ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[1]       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[1]       ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[2]       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[2]       ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[3]       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[3]       ; regout           ;
; |serial_uart_top|deal:inst2|WideOr8~17                          ; |serial_uart_top|deal:inst2|WideOr8~17                          ; combout          ;
; |serial_uart_top|deal:inst2|WideOr9~19                          ; |serial_uart_top|deal:inst2|WideOr9~19                          ; combout          ;
; |serial_uart_top|deal:inst2|WideOr10~17                         ; |serial_uart_top|deal:inst2|WideOr10~17                         ; combout          ;
; |serial_uart_top|deal:inst2|WideOr11~15                         ; |serial_uart_top|deal:inst2|WideOr11~15                         ; combout          ;
; |serial_uart_top|deal:inst2|WideOr12~19                         ; |serial_uart_top|deal:inst2|WideOr12~19                         ; combout          ;
; |serial_uart_top|deal:inst2|WideOr13~15                         ; |serial_uart_top|deal:inst2|WideOr13~15                         ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[15] ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[15] ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[14] ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[14] ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[13] ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[13] ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[12] ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[12] ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~177    ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~177    ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[11] ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[11] ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[10] ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[10] ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[9]  ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[9]  ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[8]  ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[8]  ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~178    ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~178    ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[7]  ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[7]  ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[6]  ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[6]  ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[5]  ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[5]  ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[4]  ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[4]  ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~179    ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~179    ; combout          ;
; |serial_uart_top|data_led_1[6]                                  ; |serial_uart_top|data_led_1[6]                                  ; padio            ;
; |serial_uart_top|data_led_1[5]                                  ; |serial_uart_top|data_led_1[5]                                  ; padio            ;
; |serial_uart_top|data_led_1[4]                                  ; |serial_uart_top|data_led_1[4]                                  ; padio            ;
; |serial_uart_top|data_led_1[3]                                  ; |serial_uart_top|data_led_1[3]                                  ; padio            ;
; |serial_uart_top|data_led_1[2]                                  ; |serial_uart_top|data_led_1[2]                                  ; padio            ;
; |serial_uart_top|data_led_1[1]                                  ; |serial_uart_top|data_led_1[1]                                  ; padio            ;
; |serial_uart_top|data_led_1[0]                                  ; |serial_uart_top|data_led_1[0]                                  ; padio            ;
; |serial_uart_top|data_led_2[5]                                  ; |serial_uart_top|data_led_2[5]                                  ; padio            ;
; |serial_uart_top|data_led_2[4]                                  ; |serial_uart_top|data_led_2[4]                                  ; padio            ;
; |serial_uart_top|data_led_2[3]                                  ; |serial_uart_top|data_led_2[3]                                  ; padio            ;
; |serial_uart_top|data_led_2[2]                                  ; |serial_uart_top|data_led_2[2]                                  ; padio            ;
; |serial_uart_top|data_led_2[1]                                  ; |serial_uart_top|data_led_2[1]                                  ; padio            ;
; |serial_uart_top|data_led_2[0]                                  ; |serial_uart_top|data_led_2[0]                                  ; padio            ;
+-----------------------------------------------------------------+-----------------------------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu Mar 27 14:44:18 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off serial_uart_top -c serial_uart_top
Info: Using vector source file "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top/serial_uart_top.vwf"
Warning: Can't display state machine states -- register holding state machine bit "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_LOAD" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_SEND" was synthesized away
Warning: Can't display state machine states -- register holding state machine bit "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_END_SEND" was synthesized away
Warning: Ignored node in vector source file. Can't find corresponding node name "bd_clk" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "recv_bus[7]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "recv_bus[6]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "recv_bus[5]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "recv_bus[4]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "recv_bus[3]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "recv_bus[2]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "recv_bus[1]" in design.
Warning: Ignored node in vector source file. Can't find corresponding node name "recv_bus[0]" in design.
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      53.72 %
Info: Number of transitions in simulation is 9097
Info: Quartus II Simulator was successful. 0 errors, 12 warnings
    Info: Allocated 98 megabytes of memory during processing
    Info: Processing ended: Thu Mar 27 14:44:20 2008
    Info: Elapsed time: 00:00:02