serial_uart_top.sim.rpt

来自「FPGA Cycloneii 系列的」· RPT 代码 · 共 422 行 · 第 1/4 页

The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                        ;
+------------------------------------------------------------------------+------------------------------------------------------------------------+------------------+
; Node Name                                                              ; Output Port Name                                                       ; Output Port Type ;
+------------------------------------------------------------------------+------------------------------------------------------------------------+------------------+
; |serial_uart_top|uart_top:inst|counter:inst3|Add0~48                   ; |serial_uart_top|uart_top:inst|counter:inst3|Add0~48                   ; combout          ;
; |serial_uart_top|uart_top:inst|counter:inst3|Add0~48                   ; |serial_uart_top|uart_top:inst|counter:inst3|Add0~49                   ; cout             ;
; |serial_uart_top|uart_top:inst|counter:inst3|Add0~50                   ; |serial_uart_top|uart_top:inst|counter:inst3|Add0~50                   ; combout          ;
; |serial_uart_top|uart_top:inst|counter:inst3|Add0~50                   ; |serial_uart_top|uart_top:inst|counter:inst3|Add0~51                   ; cout             ;
; |serial_uart_top|uart_top:inst|counter:inst3|Add0~52                   ; |serial_uart_top|uart_top:inst|counter:inst3|Add0~52                   ; combout          ;
; |serial_uart_top|uart_top:inst|counter:inst3|Add0~52                   ; |serial_uart_top|uart_top:inst|counter:inst3|Add0~53                   ; cout             ;
; |serial_uart_top|uart_top:inst|counter:inst3|Add0~54                   ; |serial_uart_top|uart_top:inst|counter:inst3|Add0~54                   ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~192             ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~192             ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~192             ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~193             ; cout             ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~194             ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~194             ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~194             ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~195             ; cout             ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~196             ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~196             ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~196             ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~197             ; cout             ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~198             ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Add0~198             ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv                     ; |serial_uart_top|uart_top:inst|uart_core:inst|recv                     ; regout           ;
; |serial_uart_top|deal:inst2|data_led_2[6]                              ; |serial_uart_top|deal:inst2|data_led_2[6]                              ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_RECV     ; |serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_RECV     ; regout           ;
; |serial_uart_top|uart_top:inst|counter:inst3|overflow                  ; |serial_uart_top|uart_top:inst|counter:inst3|overflow                  ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_END_RECV ; |serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_END_RECV ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector18~55            ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector18~55            ; combout          ;
; |serial_uart_top|uart_top:inst|detector:inst9|new_data                 ; |serial_uart_top|uart_top:inst|detector:inst9|new_data                 ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_IDLE     ; |serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_IDLE     ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector10~152           ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector10~152           ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector10~153           ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector10~153           ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|ce_parts                 ; |serial_uart_top|uart_top:inst|uart_core:inst|ce_parts                 ; regout           ;
; |serial_uart_top|uart_top:inst|counter:inst3|counter[3]                ; |serial_uart_top|uart_top:inst|counter:inst3|counter[3]                ; regout           ;
; |serial_uart_top|uart_top:inst|counter:inst3|counter[1]                ; |serial_uart_top|uart_top:inst|counter:inst3|counter[1]                ; regout           ;
; |serial_uart_top|uart_top:inst|counter:inst3|counter[2]                ; |serial_uart_top|uart_top:inst|counter:inst3|counter[2]                ; regout           ;
; |serial_uart_top|uart_top:inst|counter:inst3|counter[0]                ; |serial_uart_top|uart_top:inst|counter:inst3|counter[0]                ; regout           ;
; |serial_uart_top|uart_top:inst|counter:inst3|always0~46                ; |serial_uart_top|uart_top:inst|counter:inst3|always0~46                ; combout          ;
; |serial_uart_top|uart_top:inst|counter:inst3|always0~47                ; |serial_uart_top|uart_top:inst|counter:inst3|always0~47                ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|reset_parts              ; |serial_uart_top|uart_top:inst|uart_core:inst|reset_parts              ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector10~154           ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector10~154           ; combout          ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[5]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[5]           ; regout           ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[4]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[4]           ; regout           ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[3]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[3]           ; regout           ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[2]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[2]           ; regout           ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[9]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[9]           ; regout           ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[8]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[8]           ; regout           ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[7]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[7]           ; regout           ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[6]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[6]           ; regout           ;
; |serial_uart_top|uart_top:inst|detector:inst9|state                    ; |serial_uart_top|uart_top:inst|detector:inst9|state                    ; regout           ;
; |serial_uart_top|uart_top:inst|detector:inst9|always0~0                ; |serial_uart_top|uart_top:inst|detector:inst9|always0~0                ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|reset_dt                 ; |serial_uart_top|uart_top:inst|uart_core:inst|reset_dt                 ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector11~40            ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector11~40            ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector1~62             ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector1~62             ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector1~63             ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector1~63             ; combout          ;
; |serial_uart_top|uart_top:inst|counter:inst3|always0~48                ; |serial_uart_top|uart_top:inst|counter:inst3|always0~48                ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|indicator            ; |serial_uart_top|uart_top:inst|bd_generator:inst5|indicator            ; regout           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector0~86             ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector0~86             ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector0~87             ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector0~87             ; combout          ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[1]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[1]           ; regout           ;
; |serial_uart_top|uart_top:inst|detector:inst9|state~162                ; |serial_uart_top|uart_top:inst|detector:inst9|state~162                ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|Selector16~51            ; |serial_uart_top|uart_top:inst|uart_core:inst|Selector16~51            ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[1]         ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[1]         ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~180           ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~180           ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[0]         ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[0]         ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[3]         ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[3]         ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[2]         ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count[2]         ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal1~90            ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal1~90            ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~181           ; |serial_uart_top|uart_top:inst|bd_generator:inst5|Equal0~181           ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|indicator~193        ; |serial_uart_top|uart_top:inst|bd_generator:inst5|indicator~193        ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|indicator~194        ; |serial_uart_top|uart_top:inst|bd_generator:inst5|indicator~194        ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|indicator~195        ; |serial_uart_top|uart_top:inst|bd_generator:inst5|indicator~195        ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|bd_out               ; |serial_uart_top|uart_top:inst|bd_generator:inst5|bd_out               ; regout           ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[0]           ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[0]           ; regout           ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count~618        ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count~618        ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count~619        ; |serial_uart_top|uart_top:inst|bd_generator:inst5|clk_count~619        ; combout          ;
; |serial_uart_top|uart_top:inst|bd_generator:inst5|bd_out~97            ; |serial_uart_top|uart_top:inst|bd_generator:inst5|bd_out~97            ; combout          ;
; |serial_uart_top|uart_top:inst|counter:inst3|counter~102               ; |serial_uart_top|uart_top:inst|counter:inst3|counter~102               ; combout          ;
; |serial_uart_top|uart_top:inst|counter:inst3|counter~103               ; |serial_uart_top|uart_top:inst|counter:inst3|counter~103               ; combout          ;
; |serial_uart_top|uart_top:inst|switcher:inst4|dout                     ; |serial_uart_top|uart_top:inst|switcher:inst4|dout                     ; combout          ;
; |serial_uart_top|uart_top:inst|switcher:inst6|dout                     ; |serial_uart_top|uart_top:inst|switcher:inst6|dout                     ; combout          ;
; |serial_uart_top|recv                                                  ; |serial_uart_top|recv                                                  ; padio            ;
; |serial_uart_top|data_led_2[6]                                         ; |serial_uart_top|data_led_2[6]                                         ; padio            ;
; |serial_uart_top|clk                                                   ; |serial_uart_top|clk~corein                                            ; combout          ;
; |serial_uart_top|RXD                                                   ; |serial_uart_top|RXD~corein                                            ; combout          ;
; |serial_uart_top|uart_top:inst|switcher:inst4|dout~clkctrl             ; |serial_uart_top|uart_top:inst|switcher:inst4|dout~clkctrl             ; outclk           ;
; |serial_uart_top|uart_top:inst|switcher:inst6|dout~clkctrl             ; |serial_uart_top|uart_top:inst|switcher:inst6|dout~clkctrl             ; outclk           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv~clkctrl             ; |serial_uart_top|uart_top:inst|uart_core:inst|recv~clkctrl             ; outclk           ;
; |serial_uart_top|clk~clkctrl                                           ; |serial_uart_top|clk~clkctrl                                           ; outclk           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|reset_parts~clkctrl      ; |serial_uart_top|uart_top:inst|uart_core:inst|reset_parts~clkctrl      ; outclk           ;
; |serial_uart_top|uart_top:inst|uart_core:inst|reset_dt~clkctrl         ; |serial_uart_top|uart_top:inst|uart_core:inst|reset_dt~clkctrl         ; outclk           ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[6]~feeder    ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[6]~feeder    ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[4]~feeder       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[4]~feeder       ; combout          ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[5]~feeder    ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[5]~feeder    ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[5]~feeder       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[5]~feeder       ; combout          ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[4]~feeder    ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[4]~feeder    ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[6]~feeder       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[6]~feeder       ; combout          ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[3]~feeder    ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[3]~feeder    ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[7]~feeder       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[7]~feeder       ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[0]~feeder       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[0]~feeder       ; combout          ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[9]~feeder    ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[9]~feeder    ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[1]~feeder       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[1]~feeder       ; combout          ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[8]~feeder    ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[8]~feeder    ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[2]~feeder       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[2]~feeder       ; combout          ;
; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[7]~feeder    ; |serial_uart_top|uart_top:inst|shift_reg:inst13|shift_out[7]~feeder    ; combout          ;
; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[3]~feeder       ; |serial_uart_top|uart_top:inst|uart_core:inst|recv_bus[3]~feeder       ; combout          ;