serial_uart_top.map.rpt

来自「FPGA Cycloneii 系列的」· RPT 代码 · 共 631 行 · 第 1/4 页

Info (10041): Inferred latch for "FIFO1_amp[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_amp[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_amp[6]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_time[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_time[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_time[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_time[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_time[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_amp[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_amp[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_amp[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_amp[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_amp[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_amp[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_amp[6]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_time[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_time[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_time[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_time[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO2_time[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_amp[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_amp[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_amp[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_amp[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_amp[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_amp[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_amp[6]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_time[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_time[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_time[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_time[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO3_time[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_amp[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_amp[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_amp[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_amp[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_amp[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_amp[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_amp[6]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_time[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_time[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_time[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_time[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO4_time[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_amp[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_amp[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_amp[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_amp[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_amp[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_amp[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_amp[6]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_time[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_time[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_time[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_time[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO5_time[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_amp[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_amp[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_amp[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_amp[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_amp[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_amp[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_amp[6]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_time[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_time[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_time[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_time[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO6_time[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[6]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[7]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[8]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[9]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[10]" at instruc2main.v(79)
Info (10041): Inferred latch for "Row_dis_delay[11]" at instruc2main.v(79)
Info (10041): Inferred latch for "Rayleigh_MP[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "Rayleigh_MP[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "Rayleigh_MP[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "Rayleigh_MP[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "Rayleigh_MP[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "Rayleigh_MP[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "Lognormal[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "Lognormal[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "Lognormal[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "Lognormal[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "Lognormal[4]" at instruc2main.v(79)
Info: Elaborating entity "get" for hierarchy "get:inst5"
Warning (10230): Verilog HDL assignment warning at get.v(56): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at get.v(62): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at get.v(67): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at get.v(72): truncated value with size 32 to match size of target (3)
Info: Clock multiplexers have been protected
Info: Duplicate registers merged to single register
    Info: Duplicate register "uart_top:inst|uart_core:inst|sel_pv" merged to single register "uart_top:inst|uart_core:inst|sel_si"
Info: State machine "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state" contains 6 states
Info: Selected Auto state machine encoding method for state machine "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state"
Info: Encoding result for state machine "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state"
    Info: Completed encoding using 6 state bits
        Info: Encoded state bit "uart_top:inst|uart_core:inst|uart_state.UART_END_RECV"
        Info: Encoded state bit "uart_top:inst|uart_core:inst|uart_state.UART_RECV"
        Info: Encoded state bit "uart_top:inst|uart_core:inst|uart_state.UART_LOAD"
        Info: Encoded state bit "uart_top:inst|uart_core:inst|uart_state.UART_SEND"
        Info: Encoded state bit "uart_top:inst|uart_core:inst|uart_state.UART_END_SEND"
        Info: Encoded state bit "uart_top:inst|uart_core:inst|uart_state.UART_IDLE"
    Info: State "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_IDLE" uses code string "000000"
    Info: State "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_END_SEND" uses code string "000011"
    Info: State "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_SEND" uses code string "000101"
    Info: State "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_LOAD" uses code string "001001"
    Info: State "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_RECV" uses code string "010001"
    Info: State "|serial_uart_top|uart_top:inst|uart_core:inst|uart_state.UART_END_RECV" uses code string "100001"
Warning: Reduced register "uart_top:inst|uart_core:inst|uart_state.UART_LOAD" with stuck data_in port to stuck value GND
Warning: No clock transition on "uart_top:inst|uart_core:inst|si_count[3]" register due to stuck clock or clock enable
Warning: Reduced register "uart_top:inst|uart_core:inst|si_count[3]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "uart_top:inst|uart_core:inst|si_count[2]" register due to stuck clock or clock enable
Warning: Reduced register "uart_top:inst|uart_core:inst|si_count[2]" with stuck clock_enable port to stuck value GND
Warning: No clock transition on "uart_top:inst|uart_core:inst|si_count[1]" register due to stuck clock or clock enable
Warning: Reduced register "uart_top:inst|uart_core:inst|si_count[1]" with stuck clock_enable port to stuck value GND
Warning: Reduced register "uart_top:inst|uart_core:inst|si_count[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "uart_top:inst|uart_core:inst|uart_state.UART_SEND" with stuck data_in port to stuck value GND
Warning: Reduced register "uart_top:inst|uart_core:inst|uart_state.UART_END_SEND" with stuck data_in port to stuck value GND
Warning: Reduced register "uart_top:inst|uart_core:inst|sel_clk" with stuck data_in port to stuck value GND
Info: Power-up level of register "uart_top:inst|uart_core:inst|sel_si" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "uart_top:inst|uart_core:inst|sel_si" with stuck data_in port to stuck value VCC
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "data_led_3[6]" stuck at VCC
    Warning: Pin "data_led_3[2]" stuck at GND
    Warning: Pin "data_led_3[1]" stuck at GND
Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below.
    Info: Register "inst/inst/uart_state~35" lost all its fanouts during netlist optimizations.
    Info: Register "inst/inst/uart_state~36" lost all its fanouts during netlist optimizations.
    Info: Register "inst/inst/uart_state~37" lost all its fanouts during netlist optimizations.
Info: Found the following redundant logic cells in design
    Info: Logic cell "uart_top:inst|switcher:inst4|dout"
    Info: Logic cell "uart_top:inst|switcher:inst6|dout"
Info: Generated suppressed messages file C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.map.smsg
Info: Implemented 191 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 37 output pins
    Info: Implemented 152 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings
    Info: Allocated 140 megabytes of memory during processing
    Info: Processing ended: Fri Mar 28 17:19:04 2008
    Info: Elapsed time: 00:00:05


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/serial_uart_top_new/serial_uart_top_new/serial_uart_top.map.smsg.