serial_uart_top.map.rpt

来自「FPGA Cycloneii 系列的」· RPT 代码 · 共 631 行 · 第 1/4 页

; TOTAL_BIT      ; 1100  ; Unsigned Binary                                  ;
; UART_IDLE      ; 000   ; Unsigned Binary                                  ;
; UART_LOAD      ; 001   ; Unsigned Binary                                  ;
; UART_SEND      ; 010   ; Unsigned Binary                                  ;
; UART_END_SEND  ; 011   ; Unsigned Binary                                  ;
; UART_RECV      ; 100   ; Unsigned Binary                                  ;
; UART_END_RECV  ; 101   ; Unsigned Binary                                  ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:inst|parity_verifier:inst2 ;
+----------------+-------+---------------------------------------------------------+
; Parameter Name ; Value ; Type                                                    ;
+----------------+-------+---------------------------------------------------------+
; DATA_LENGTH    ; 8     ; Signed Integer                                          ;
; PARITY_ODD     ; 0     ; Signed Integer                                          ;
; PARITY_EVEN    ; 1     ; Signed Integer                                          ;
+----------------+-------+---------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:inst|detector:inst9 ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type                                             ;
+----------------+-------+--------------------------------------------------+
; dt_unlock      ; 0     ; Unsigned Binary                                  ;
; dt_lock        ; 1     ; Unsigned Binary                                  ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:inst|bd_generator:inst5 ;
+----------------+-------+------------------------------------------------------+
; Parameter Name ; Value ; Type                                                 ;
+----------------+-------+------------------------------------------------------+
; start_count    ; 434   ; Signed Integer                                       ;
; end_count      ; 868   ; Signed Integer                                       ;
+----------------+-------+------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: uart_top:inst|counter:inst3 ;
+----------------+-------+-------------------------------------------------+
; Parameter Name ; Value ; Type                                            ;
+----------------+-------+-------------------------------------------------+
; MAX_COUNT      ; 10    ; Signed Integer                                  ;
+----------------+-------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Fri Mar 28 17:18:59 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off serial_uart_top -c serial_uart_top
Info: Found 1 design units, including 1 entities, in source file serial_uart_top.bdf
    Info: Found entity 1: serial_uart_top
Info: Found 1 design units, including 1 entities, in source file uart_top.bdf
    Info: Found entity 1: uart_top
Info: Found 1 design units, including 1 entities, in source file switcher_bus.v
    Info: Found entity 1: switcher_bus
Info: Found 1 design units, including 1 entities, in source file switcher.v
    Info: Found entity 1: switcher
Info: Found 1 design units, including 1 entities, in source file shift_reg.v
    Info: Found entity 1: shift_reg
Info: Found 1 design units, including 1 entities, in source file detector.v
    Info: Found entity 1: detector
Info: Found 1 design units, including 1 entities, in source file parity_verifier.v
    Info: Found entity 1: parity_verifier
Info: Found 1 design units, including 1 entities, in source file bd_generator.v
    Info: Found entity 1: bd_generator
Info: Found 1 design units, including 1 entities, in source file counter.v
    Info: Found entity 1: counter
Info: Found 1 design units, including 1 entities, in source file uart_core.v
    Info: Found entity 1: uart_core
Info: Found 1 design units, including 1 entities, in source file deal.v
    Info: Found entity 1: deal
Info: Found 1 design units, including 1 entities, in source file get.v
    Info: Found entity 1: get
Info: Found 1 design units, including 1 entities, in source file instruc2main.v
    Info: Found entity 1: instruc2main
Info: Found 1 design units, including 1 entities, in source file deal1.v
    Info: Found entity 1: deal1
Info: Found 1 design units, including 1 entities, in source file dealx.v
    Info: Found entity 1: dealx
Info: Elaborating entity "serial_uart_top" for the top level hierarchy
Info: Elaborating entity "uart_top" for hierarchy "uart_top:inst"
Info: Elaborating entity "switcher" for hierarchy "uart_top:inst|switcher:inst10"
Info: Elaborating entity "uart_core" for hierarchy "uart_top:inst|uart_core:inst"
Warning (10235): Verilog HDL Always Construct warning at uart_core.v(89): variable "send_buf" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10230): Verilog HDL assignment warning at uart_core.v(129): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "parity_verifier" for hierarchy "uart_top:inst|parity_verifier:inst2"
Warning (10240): Verilog HDL Always Construct warning at parity_verifier.v(42): inferring latch(es) for variable "parity", which holds its previous value in one or more paths through the always construct
Info: Elaborating entity "switcher_bus" for hierarchy "uart_top:inst|switcher_bus:inst1"
Info: Elaborating entity "detector" for hierarchy "uart_top:inst|detector:inst9"
Info: Elaborating entity "shift_reg" for hierarchy "uart_top:inst|shift_reg:inst13"
Info: Elaborating entity "bd_generator" for hierarchy "uart_top:inst|bd_generator:inst5"
Warning (10230): Verilog HDL assignment warning at bd_generator.v(57): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at bd_generator.v(68): truncated value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at bd_generator.v(71): truncated value with size 32 to match size of target (16)
Info: Elaborating entity "counter" for hierarchy "uart_top:inst|counter:inst3"
Info: Elaborating entity "deal" for hierarchy "deal:inst2"
Warning (10230): Verilog HDL assignment warning at deal.v(48): truncated value with size 32 to match size of target (4)
Info: Elaborating entity "instruc2main" for hierarchy "instruc2main:inst6"
Warning (10270): Verilog HDL Case Statement warning at instruc2main.v(94): incomplete case statement has no default case item
Warning (10230): Verilog HDL assignment warning at instruc2main.v(129): truncated value with size 32 to match size of target (12)
Warning (10270): Verilog HDL Case Statement warning at instruc2main.v(82): incomplete case statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "Lognormal", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "Rayleigh_MP", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "Row_dis_delay", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO6_time", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO6_amp", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO5_time", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO5_amp", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO4_time", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO4_amp", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO3_time", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO3_amp", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO2_time", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO2_amp", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO1_time", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "FIFO1_amp", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "Gauss_P", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at instruc2main.v(79): inferring latch(es) for variable "doppler_step", which holds its previous value in one or more paths through the always construct
Info (10041): Inferred latch for "doppler_step[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[6]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[7]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[8]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[9]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[10]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[11]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[12]" at instruc2main.v(79)
Info (10041): Inferred latch for "doppler_step[13]" at instruc2main.v(79)
Info (10041): Inferred latch for "Gauss_P[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "Gauss_P[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "Gauss_P[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "Gauss_P[3]" at instruc2main.v(79)
Info (10041): Inferred latch for "Gauss_P[4]" at instruc2main.v(79)
Info (10041): Inferred latch for "Gauss_P[5]" at instruc2main.v(79)
Info (10041): Inferred latch for "Gauss_P[6]" at instruc2main.v(79)
Info (10041): Inferred latch for "Gauss_P[7]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_amp[0]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_amp[1]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_amp[2]" at instruc2main.v(79)
Info (10041): Inferred latch for "FIFO1_amp[3]" at instruc2main.v(79)