sin_sample.cdf

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· CDF 代码 · 共 14 行

/* Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version */
JedecChain;
	FileRevision(JESD32A);
	DefaultMfr(6E);

	P ActionCode(Cfg)
		Device PartName(EPCS4) Path("C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/") File("sin_sample.pof") MfrSpec(OpMask(1) Child_OpMask(1 1));

ChainEnd;

AlteraBegin;
	ChainType(asc);
AlteraEnd;