prev_cmp_sin_sample.tan.qmsg

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "ITDB_TH_RESULT" "sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[3\] altera_internal_jtag~TDIUTAP altera_internal_jtag~TCKUTAP 1.023 ns register " "Info: th for register \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[3\]\" (data pin = \"altera_internal_jtag~TDIUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.023 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.915 ns + Longest register " "Info: + Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.915 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.315 ns) + CELL(0.000 ns) 3.315 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 142 " "Info: 2: + IC(3.315 ns) + CELL(0.000 ns) = 3.315 ns; Loc. = CLKCTRL_G0; Fanout = 142; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.315 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.602 ns) 4.915 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[3\] 3 REG LCFF_X34_Y13_N11 1 " "Info: 3: + IC(0.998 ns) + CELL(0.602 ns) = 4.915 ns; Loc. = LCFF_X34_Y13_N11; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 12.25 % ) " "Info: Total cell delay = 0.602 ns ( 12.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.313 ns ( 87.75 % ) " "Info: Total interconnect delay = 4.313 ns ( 87.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } { 0.000ns 3.315ns 0.998ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.286 ns + " "Info: + Micro hold delay of destination is 0.286 ns" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.178 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDIUTAP 1 PIN JTAG_X1_Y14_N0 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 11; PIN Node = 'altera_internal_jtag~TDIUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDIUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.760 ns) + CELL(0.322 ns) 4.082 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR~957 2 COMB LCCOMB_X34_Y13_N10 1 " "Info: 2: + IC(3.760 ns) + CELL(0.322 ns) = 4.082 ns; Loc. = LCCOMB_X34_Y13_N10; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR~957'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.082 ns" { altera_internal_jtag~TDIUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~957 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 4.178 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[3\] 3 REG LCFF_X34_Y13_N11 1 " "Info: 3: + IC(0.000 ns) + CELL(0.096 ns) = 4.178 ns; Loc. = LCFF_X34_Y13_N11; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[3\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~957 sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.418 ns ( 10.00 % ) " "Info: Total cell delay = 0.418 ns ( 10.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.760 ns ( 90.00 % ) " "Info: Total interconnect delay = 3.760 ns ( 90.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.178 ns" { altera_internal_jtag~TDIUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~957 sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.178 ns" { altera_internal_jtag~TDIUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~957 sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } { 0.000ns 3.760ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } { 0.000ns 3.315ns 0.998ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.178 ns" { altera_internal_jtag~TDIUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~957 sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.178 ns" { altera_internal_jtag~TDIUTAP sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR~957 sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[3] } { 0.000ns 3.760ns 0.000ns } { 0.000ns 0.322ns 0.096ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "111 " "Info: Allocated 111 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 24 14:26:03 2008 " "Info: Processing ended: Mon Mar 24 14:26:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}