prev_cmp_sin_sample.tan.qmsg

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 1.420 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 1.420 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.374 ns + Longest pin register " "Info: + Longest pin to register delay is 6.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y14_N0 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 22; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.667 ns) + CELL(0.512 ns) 5.179 ns sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21 2 COMB LCCOMB_X36_Y13_N30 2 " "Info: 2: + IC(4.667 ns) + CELL(0.512 ns) = 5.179 ns; Loc. = LCCOMB_X36_Y13_N30; Fanout = 2; COMB Node = 'sld_hub:sld_hub_inst\|IRF_ENA_ENABLE~21'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.179 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 381 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.758 ns) 6.374 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 3 REG LCFF_X37_Y13_N9 3 " "Info: 3: + IC(0.437 ns) + CELL(0.758 ns) = 6.374 ns; Loc. = LCFF_X37_Y13_N9; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.195 ns" { sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.270 ns ( 19.92 % ) " "Info: Total cell delay = 1.270 ns ( 19.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.104 ns ( 80.08 % ) " "Info: Total interconnect delay = 5.104 ns ( 80.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.374 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.374 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.667ns 0.437ns } { 0.000ns 0.512ns 0.758ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.916 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.315 ns) + CELL(0.000 ns) 3.315 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 142 " "Info: 2: + IC(3.315 ns) + CELL(0.000 ns) = 3.315 ns; Loc. = CLKCTRL_G0; Fanout = 142; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.315 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.602 ns) 4.916 ns sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\] 3 REG LCFF_X37_Y13_N9 3 " "Info: 3: + IC(0.999 ns) + CELL(0.602 ns) = 4.916 ns; Loc. = LCFF_X37_Y13_N9; Fanout = 3; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:IRF_ENA_0\|Q\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 12.25 % ) " "Info: Total cell delay = 0.602 ns ( 12.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.314 ns ( 87.75 % ) " "Info: Total interconnect delay = 4.314 ns ( 87.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 3.315ns 0.999ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.374 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.374 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|IRF_ENA_ENABLE~21 sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 4.667ns 0.437ns } { 0.000ns 0.512ns 0.758ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0] } { 0.000ns 3.315ns 0.999ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "inclk0 data_da\[10\] lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[10\] 9.667 ns memory " "Info: tco from clock \"inclk0\" to destination pin \"data_da\[10\]\" through memory \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[10\]\" is 9.667 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk0 source 4.009 ns + Longest memory " "Info: + Longest clock path from clock \"inclk0\" to source memory is 4.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns inclk0 1 CLK PIN_F20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_F20; Fanout = 24; CLK Node = 'inclk0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } } { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 72 -264 -96 88 "inclk0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.421 ns) + CELL(0.724 ns) 4.009 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[10\] 2 MEM M4K_X41_Y13 2 " "Info: 2: + IC(2.421 ns) + CELL(0.724 ns) = 4.009 ns; Loc. = M4K_X41_Y13; Fanout = 2; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[10\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.145 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] } "NODE_NAME" } } { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.588 ns ( 39.61 % ) " "Info: Total cell delay = 1.588 ns ( 39.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.421 ns ( 60.39 % ) " "Info: Total interconnect delay = 2.421 ns ( 60.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.009 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.009 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] } { 0.000ns 0.000ns 2.421ns } { 0.000ns 0.864ns 0.724ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.234 ns + " "Info: + Micro clock to output delay of source is 0.234 ns" {  } { { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.424 ns + Longest memory pin " "Info: + Longest memory to pin delay is 5.424 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.098 ns) 0.098 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[10\] 1 MEM M4K_X41_Y13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.098 ns) = 0.098 ns; Loc. = M4K_X41_Y13; Fanout = 2; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[10\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] } "NODE_NAME" } } { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.331 ns) + CELL(2.995 ns) 5.424 ns data_da\[10\] 2 PIN PIN_E19 0 " "Info: 2: + IC(2.331 ns) + CELL(2.995 ns) = 5.424 ns; Loc. = PIN_E19; Fanout = 0; PIN Node = 'data_da\[10\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.326 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] data_da[10] } "NODE_NAME" } } { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 80 728 904 96 "data_da\[13..0\]" "" } { 88 656 716 160 "data_da\[13..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.093 ns ( 57.02 % ) " "Info: Total cell delay = 3.093 ns ( 57.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.331 ns ( 42.98 % ) " "Info: Total interconnect delay = 2.331 ns ( 42.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.424 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] data_da[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.424 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] data_da[10] } { 0.000ns 2.331ns } { 0.098ns 2.995ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.009 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.009 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] } { 0.000ns 0.000ns 2.421ns } { 0.000ns 0.864ns 0.724ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.424 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] data_da[10] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.424 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[10] data_da[10] } { 0.000ns 2.331ns } { 0.098ns 2.995ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "altera_internal_jtag~TDO altera_reserved_tdo 2.810 ns Longest " "Info: Longest tpd from source pin \"altera_internal_jtag~TDO\" to destination pin \"altera_reserved_tdo\" is 2.810 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TDO 1 PIN JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; PIN Node = 'altera_internal_jtag~TDO'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.810 ns) 2.810 ns altera_reserved_tdo 2 PIN PIN_L5 0 " "Info: 2: + IC(0.000 ns) + CELL(2.810 ns) = 2.810 ns; Loc. = PIN_L5; Fanout = 0; PIN Node = 'altera_reserved_tdo'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.810 ns ( 100.00 % ) " "Info: Total cell delay = 2.810 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.810 ns" { altera_internal_jtag~TDO altera_reserved_tdo } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.810 ns" { altera_internal_jtag~TDO altera_reserved_tdo } { 0.000ns 0.000ns } { 0.000ns 2.810ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}