prev_cmp_sin_sample.tan.qmsg

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· QMSG 代码 · 共 12 行 · 第 1/5 页

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "inclk0 " "Info: Assuming node \"inclk0\" is an undefined clock" {  } { { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 72 -264 -96 88 "inclk0" "" } } } } { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "inclk0" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "altera_internal_jtag~TCKUTAP " "Info: Assuming node \"altera_internal_jtag~TCKUTAP\" is an undefined clock" {  } { { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TCKUTAP" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "inclk0 memory memory lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|ram_block3a0~porta_address_reg0 lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[0\] 163.03 MHz Internal " "Info: Clock \"inclk0\" Internal fmax is restricted to 163.03 MHz between source memory \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|ram_block3a0~porta_address_reg0\" and destination memory \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[0\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "3.067 ns 3.067 ns 6.134 ns " "Info: fmax restricted to Clock High delay (3.067 ns) plus Clock Low delay (3.067 ns) : restricted to 6.134 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.267 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.267 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|ram_block3a0~porta_address_reg0 1 MEM M4K_X41_Y13 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X41_Y13; Fanout = 14; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.267 ns) 3.267 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[0\] 2 MEM M4K_X41_Y13 2 " "Info: 2: + IC(0.000 ns) + CELL(3.267 ns) = 3.267 ns; Loc. = M4K_X41_Y13; Fanout = 2; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.267 ns ( 100.00 % ) " "Info: Total cell delay = 3.267 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.267ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.023 ns - Smallest " "Info: - Smallest clock skew is -0.023 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk0 destination 4.009 ns + Shortest memory " "Info: + Shortest clock path from clock \"inclk0\" to destination memory is 4.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns inclk0 1 CLK PIN_F20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_F20; Fanout = 24; CLK Node = 'inclk0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } } { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 72 -264 -96 88 "inclk0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.421 ns) + CELL(0.724 ns) 4.009 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[0\] 2 MEM M4K_X41_Y13 2 " "Info: 2: + IC(2.421 ns) + CELL(0.724 ns) = 4.009 ns; Loc. = M4K_X41_Y13; Fanout = 2; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|q_a\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.145 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } "NODE_NAME" } } { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 43 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.588 ns ( 39.61 % ) " "Info: Total cell delay = 1.588 ns ( 39.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.421 ns ( 60.39 % ) " "Info: Total interconnect delay = 2.421 ns ( 60.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.009 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.009 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } { 0.000ns 0.000ns 2.421ns } { 0.000ns 0.864ns 0.724ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "inclk0 source 4.032 ns - Longest memory " "Info: - Longest clock path from clock \"inclk0\" to source memory is 4.032 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns inclk0 1 CLK PIN_F20 24 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_F20; Fanout = 24; CLK Node = 'inclk0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { inclk0 } "NODE_NAME" } } { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 72 -264 -96 88 "inclk0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.421 ns) + CELL(0.747 ns) 4.032 ns lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|ram_block3a0~porta_address_reg0 2 MEM M4K_X41_Y13 14 " "Info: 2: + IC(2.421 ns) + CELL(0.747 ns) = 4.032 ns; Loc. = M4K_X41_Y13; Fanout = 14; MEM Node = 'lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\|ram_block3a0~porta_address_reg0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.168 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 48 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.611 ns ( 39.96 % ) " "Info: Total cell delay = 1.611 ns ( 39.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.421 ns ( 60.04 % ) " "Info: Total interconnect delay = 2.421 ns ( 60.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.032 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.032 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 2.421ns } { 0.000ns 0.864ns 0.747ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.009 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.009 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } { 0.000ns 0.000ns 2.421ns } { 0.000ns 0.864ns 0.724ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.032 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.032 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 2.421ns } { 0.000ns 0.864ns 0.747ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.234 ns + " "Info: + Micro clock to output delay of source is 0.234 ns" {  } { { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 48 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.040 ns + " "Info: + Micro setup delay of destination is 0.040 ns" {  } { { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 43 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.267 ns" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } { 0.000ns 0.000ns } { 0.000ns 3.267ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.009 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.009 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } { 0.000ns 0.000ns 2.421ns } { 0.000ns 0.864ns 0.724ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.032 ns" { inclk0 lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.032 ns" { inclk0 inclk0~combout lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|ram_block3a0~porta_address_reg0 } { 0.000ns 0.000ns 2.421ns } { 0.000ns 0.864ns 0.747ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { lpm_rom0:inst|altsyncram:altsyncram_component|altsyncram_mea1:auto_generated|altsyncram_am92:altsyncram1|q_a[0] } { 0.000ns } { 0.098ns } "" } } { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 43 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] register sld_hub:sld_hub_inst\|hub_tdo_reg 159.03 MHz 6.288 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 159.03 MHz between source register \"sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo_reg\" (period= 6.288 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.906 ns + Longest register register " "Info: + Longest register to register delay is 2.906 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 1 REG LCFF_X34_Y13_N21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X34_Y13_N21; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.870 ns) + CELL(0.541 ns) 1.411 ns sld_hub:sld_hub_inst\|hub_tdo_reg~292 2 COMB LCCOMB_X36_Y13_N16 1 " "Info: 2: + IC(0.870 ns) + CELL(0.541 ns) = 1.411 ns; Loc. = LCCOMB_X36_Y13_N16; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~292'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.411 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~292 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.301 ns) + CELL(0.322 ns) 2.034 ns sld_hub:sld_hub_inst\|hub_tdo_reg~293 3 COMB LCCOMB_X36_Y13_N24 1 " "Info: 3: + IC(0.301 ns) + CELL(0.322 ns) = 2.034 ns; Loc. = LCCOMB_X36_Y13_N24; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~293'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.623 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.319 ns) + CELL(0.457 ns) 2.810 ns sld_hub:sld_hub_inst\|hub_tdo_reg~295 4 COMB LCCOMB_X36_Y13_N6 1 " "Info: 4: + IC(0.319 ns) + CELL(0.457 ns) = 2.810 ns; Loc. = LCCOMB_X36_Y13_N6; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg~295'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.776 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg~295 } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.096 ns) 2.906 ns sld_hub:sld_hub_inst\|hub_tdo_reg 5 REG LCFF_X36_Y13_N7 2 " "Info: 5: + IC(0.000 ns) + CELL(0.096 ns) = 2.906 ns; Loc. = LCFF_X36_Y13_N7; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.096 ns" { sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.416 ns ( 48.73 % ) " "Info: Total cell delay = 1.416 ns ( 48.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.490 ns ( 51.27 % ) " "Info: Total interconnect delay = 1.490 ns ( 51.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.906 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.906 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 0.870ns 0.301ns 0.319ns 0.000ns } { 0.000ns 0.541ns 0.322ns 0.457ns 0.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.001 ns - Smallest " "Info: - Smallest clock skew is 0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 4.916 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 4.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.315 ns) + CELL(0.000 ns) 3.315 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 142 " "Info: 2: + IC(3.315 ns) + CELL(0.000 ns) = 3.315 ns; Loc. = CLKCTRL_G0; Fanout = 142; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.315 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.999 ns) + CELL(0.602 ns) 4.916 ns sld_hub:sld_hub_inst\|hub_tdo_reg 3 REG LCFF_X36_Y13_N7 2 " "Info: 3: + IC(0.999 ns) + CELL(0.602 ns) = 4.916 ns; Loc. = LCFF_X36_Y13_N7; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo_reg'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.601 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 12.25 % ) " "Info: Total cell delay = 0.602 ns ( 12.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.314 ns ( 87.75 % ) " "Info: Total interconnect delay = 4.314 ns ( 87.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 3.315ns 0.999ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 4.915 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 4.915 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y14_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y14_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.315 ns) + CELL(0.000 ns) 3.315 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G0 142 " "Info: 2: + IC(3.315 ns) + CELL(0.000 ns) = 3.315 ns; Loc. = CLKCTRL_G0; Fanout = 142; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.315 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.602 ns) 4.915 ns sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\] 3 REG LCFF_X34_Y13_N21 1 " "Info: 3: + IC(0.998 ns) + CELL(0.602 ns) = 4.915 ns; Loc. = LCFF_X34_Y13_N21; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|sld_rom_sr:HUB_INFO_REG\|WORD_SR\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.602 ns ( 12.25 % ) " "Info: Total cell delay = 0.602 ns ( 12.25 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.313 ns ( 87.75 % ) " "Info: Total interconnect delay = 4.313 ns ( 87.75 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 3.315ns 0.998ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 3.315ns 0.999ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 3.315ns 0.998ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.277 ns + " "Info: + Micro clock to output delay of source is 0.277 ns" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.038 ns + " "Info: + Micro setup delay of destination is -0.038 ns" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 62 -1 0 } } { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.906 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.906 ns" { sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] sld_hub:sld_hub_inst|hub_tdo_reg~292 sld_hub:sld_hub_inst|hub_tdo_reg~293 sld_hub:sld_hub_inst|hub_tdo_reg~295 sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 0.870ns 0.301ns 0.319ns 0.000ns } { 0.000ns 0.541ns 0.322ns 0.457ns 0.096ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.916 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_tdo_reg } { 0.000ns 3.315ns 0.999ns } { 0.000ns 0.000ns 0.602ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.915 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0] } { 0.000ns 3.315ns 0.998ns } { 0.000ns 0.000ns 0.602ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}