prev_cmp_sin_sample.map.qmsg

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· QMSG 代码 · 共 54 行 · 第 1/3 页

{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_mea1.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_mea1.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file ../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_rom_sr-INFO_REG " "Info: Found design unit 1: sld_rom_sr-INFO_REG" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 27 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_rom_sr " "Info: Found entity 1: sld_rom_sr" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_rom_sr.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_rom_sr lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr " "Info: Elaborating entity \"sld_rom_sr\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\"" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "\\ram_rom_logic_gen:name_gen:info_rom_sr" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 631 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\|sld_rom_sr:\\ram_rom_logic_gen:name_gen:info_rom_sr\", which is child of megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 631 0 0 } } { "db/altsyncram_mea1.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_mea1.tdf" 35 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Instantiated megafunction \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "CVALUE 00000000000000 " "Info: Parameter \"CVALUE\" = \"00000000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_DATA_IN_RAM 1 " "Info: Parameter \"IS_DATA_IN_RAM\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "IS_READABLE 1 " "Info: Parameter \"IS_READABLE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_NAME 1919905024 " "Info: Parameter \"NODE_NAME\" = \"1919905024\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS 32 " "Info: Parameter \"NUMWORDS\" = \"32\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SHIFT_COUNT_BITS 4 " "Info: Parameter \"SHIFT_COUNT_BITS\" = \"4\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_WORD 14 " "Info: Parameter \"WIDTH_WORD\" = \"14\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD 5 " "Info: Parameter \"WIDTHAD\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } { { "db/altsyncram_mea1.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_mea1.tdf" 35 2 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "address_gen address_gen:inst1 " "Info: Elaborating entity \"address_gen\" for hierarchy \"address_gen:inst1\"" {  } { { "sin_sample.bdf" "inst1" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 40 96 256 136 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 address_gen.v(39) " "Warning (10230): Verilog HDL assignment warning at address_gen.v(39): truncated value with size 32 to match size of target (5)" {  } { { "address_gen.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/address_gen.v" 39 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "trans_ad_da.v 1 1 " "Warning: Using design file trans_ad_da.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 trans_ad_da " "Info: Found entity 1: trans_ad_da" {  } { { "trans_ad_da.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/trans_ad_da.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "trans_ad_da trans_ad_da:inst3 " "Info: Elaborating entity \"trans_ad_da\" for hierarchy \"trans_ad_da:inst3\"" {  } { { "sin_sample.bdf" "inst3" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 160 544 712 256 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 14 trans_ad_da.v(37) " "Warning (10230): Verilog HDL assignment warning at trans_ad_da.v(37): truncated value with size 32 to match size of target (14)" {  } { { "trans_ad_da.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/trans_ad_da.v" 37 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd 6 2 " "Info: Found 6 design units, including 2 entities, in source file ../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 HUB_PACK " "Info: Found design unit 1: HUB_PACK" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 JTAG_PACK " "Info: Found design unit 2: JTAG_PACK" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 63 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_hub-rtl " "Info: Found design unit 3: sld_hub-rtl" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 167 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_jtag_state_machine-rtl " "Info: Found design unit 4: sld_jtag_state_machine-rtl" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 1138 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_hub " "Info: Found entity 1: sld_hub" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 99 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_jtag_state_machine " "Info: Found entity 2: sld_jtag_state_machine" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 1123 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 567 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 1 " "Info: Parameter \"N_NODES\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 1 " "Info: Parameter \"N_SEL_BITS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 00001000000110000110111000000000 " "Info: Parameter \"NODE_INFO\" = \"00001000000110000110111000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 1 " "Info: Parameter \"COMPILATION_MODE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone II " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone II\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_shiftreg " "Info: Found entity 1: lpm_shiftreg" {  } { { "lpm_shiftreg.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_shiftreg.tdf" 39 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register sld_hub:sld_hub_inst " "Info: Elaborated megafunction instantiation \"sld_hub:sld_hub_inst\|lpm_shiftreg:jtag_ir_register\", which is child of megafunction instantiation \"sld_hub:sld_hub_inst\"" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_hub.vhd" 598 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "sld_hub:sld_hub_inst " "Info: Instantiated megafunction \"sld_hub:sld_hub_inst\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_VERSION 1 " "Info: Parameter \"SLD_HUB_IP_VERSION\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_HUB_IP_MINOR_VERSION 3 " "Info: Parameter \"SLD_HUB_IP_MINOR_VERSION\" = \"3\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "SLD_COMMON_IP_VERSION 0 " "Info: Parameter \"SLD_COMMON_IP_VERSION\" = \"0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODES 1 " "Info: Parameter \"N_NODES\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_SEL_BITS 1 " "Info: Parameter \"N_SEL_BITS\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "N_NODE_IR_BITS 5 " "Info: Parameter \"N_NODE_IR_BITS\" = \"5\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NODE_INFO 00001000000110000110111000000000 " "Info: Parameter \"NODE_INFO\" = \"00001000000110000110111000000000\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "COMPILATION_MODE 1 " "Info: Parameter \"COMPILATION_MODE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "DEVICE_FAMILY Cyclone II " "Info: Parameter \"DEVICE_FAMILY\" = \"Cyclone II\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/71/quartus/libraries/megafunctions/lpm_decode.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/71/quartus/libraries/megafunctions/lpm_decode.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_decode " "Info: Found entity 1: lpm_decode" {  } { { "lpm_decode.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/lpm_decode.tdf" 64 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}