prev_cmp_sin_sample.map.qmsg

来自「EP2C CYCONLY 系列的FPGA时钟测试程序」· QMSG 代码 · 共 54 行 · 第 1/3 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 24 14:25:22 2008 " "Info: Processing started: Mon Mar 24 14:25:22 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off sin_sample -c sin_sample " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sin_sample -c sin_sample" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sin_sample.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file sin_sample.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 sin_sample " "Info: Found entity 1: sin_sample" {  } { { "sin_sample.bdf" "" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "address_gen.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file address_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 address_gen " "Info: Found entity 1: address_gen" {  } { { "address_gen.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/address_gen.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ad_da.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ad_da.v" { { "Info" "ISGN_ENTITY_NAME" "1 ad_da " "Info: Found entity 1: ad_da" {  } { { "ad_da.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/ad_da.v" 24 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "sin_sample " "Info: Elaborating entity \"sin_sample\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_rom0.v 1 1 " "Warning: Using design file lpm_rom0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/lpm_rom0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:inst " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:inst\"" {  } { { "sin_sample.bdf" "inst" { Schematic "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/sin_sample.bdf" { { 48 312 472 128 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/71/quartus/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../altera/71/quartus/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 435 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:inst\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.v" "altsyncram_component" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/lpm_rom0.v" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_rom0:inst\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_rom0:inst\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.v" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/lpm_rom0.v" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_mea1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_mea1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_mea1 " "Info: Found entity 1: altsyncram_mea1" {  } { { "db/altsyncram_mea1.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_mea1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_mea1 lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated " "Info: Elaborating entity \"altsyncram_mea1\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/71/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_am92.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_am92.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_am92 " "Info: Found entity 1: altsyncram_am92" {  } { { "db/altsyncram_am92.tdf" "" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_am92.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_am92 lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1 " "Info: Elaborating entity \"altsyncram_am92\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|altsyncram_am92:altsyncram1\"" {  } { { "db/altsyncram_mea1.tdf" "altsyncram1" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_mea1.tdf" 34 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file ../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_mod_ram_rom_pack " "Info: Found design unit 1: sld_mod_ram_rom_pack" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 4 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_mod_ram_rom-rtl " "Info: Found design unit 2: sld_mod_ram_rom-rtl" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 72 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_mod_ram_rom " "Info: Found entity 1: sld_mod_ram_rom" {  } { { "../../../../../altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "C:/altera/71/quartus/libraries/megafunctions/sld_mod_ram_rom.vhd" 16 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sld_mod_ram_rom lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2 " "Info: Elaborating entity \"sld_mod_ram_rom\" for hierarchy \"lpm_rom0:inst\|altsyncram:altsyncram_component\|altsyncram_mea1:auto_generated\|sld_mod_ram_rom:mgl_prim2\"" {  } { { "db/altsyncram_mea1.tdf" "mgl_prim2" { Text "C:/Documents and Settings/Sa_Chan_S/桌面/quartus内部/sin_sample_clock/db/altsyncram_mea1.tdf" 35 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}